Lines Matching +full:17 +full:- +full:32
4 * SPDX-License-Identifier: Apache-2.0
125 #define MIO17 17
140 #define MIO32 32
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
164 #define MIO_GROUP_ETHERNET0_0_GRP_PINS 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27
165 #define MIO_GROUP_ETHERNET1_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
172 #define MIO_GROUP_SPI0_0_GRP_PINS 16, 17, 21
179 #define MIO_GROUP_SPI0_1_SS2_PINS 32
200 #define MIO_GROUP_SDIO0_0_GRP_PINS 16, 17, 18, 19, 20, 21
201 #define MIO_GROUP_SDIO0_1_GRP_PINS 28, 29, 30, 31, 32, 33
212 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
213 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
217 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23
231 #define MIO_GROUP_CAN1_2_GRP_PINS 16, 17
235 #define MIO_GROUP_CAN1_6_GRP_PINS 32, 33
254 #define MIO_GROUP_UART1_2_GRP_PINS 16, 17
258 #define MIO_GROUP_UART1_6_GRP_PINS 32, 33
276 #define MIO_GROUP_I2C1_1_GRP_PINS 16, 17
280 #define MIO_GROUP_I2C1_5_GRP_PINS 32, 33
289 #define MIO_GROUP_TTC1_0_GRP_PINS 16, 17
314 #define MIO_GROUP_GPIO0_17_GRP_PINS 17
329 #define MIO_GROUP_GPIO0_32_GRP_PINS 32
351 #define MIO_GROUP_USB0_0_GRP_PINS 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39
360 /* Iterate over each pinctrl-n phandle child */
367 * - Iterate over each pin in group and populate pinctrl_soc_pin_t
369 * - Iterate over each pin in pins and populate pinctrl_soc_pin_t