| /Zephyr-latest/dts/bindings/gpio/ |
| D | particle-gen3-header.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
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| D | sparkfun,micromod-gpio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 * An 6-pin Power Supply header. No pins on this header are exposed
17 * 2 i2c buses. Only the corresponding interrupt pin is exposed by
19 * 2 SPI buses not exposed by this binding. Only SPI CS control pin
24 * 12 General purpose pins (G0 - G11).
29 - 00 -> A0 PIN 34
30 - 01 -> A1 PIN 38
31 - 02 -> D0 PIN 10
32 - 03 -> D1/CAM_TRIG PIN 18
33 - 04 -> I2C_INT# PIN 16
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| D | nxp,pcf857x.yaml | 2 # 2023 Amrith Venkat Kesavamoorthi <amrith@mr-beam.org>
4 # SPDX-License-Identifier: Apache-2.0
6 description: PCF857x 8/16-bit I2C-based I/O expander
10 include: [i2c-device.yaml, gpio-controller.yaml]
16 - 8
17 - 16
19 int-gpios:
20 type: phandle-array
22 GPIO connected to the controller INT pin. This pin is active-low.
24 "#gpio-cells":
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| D | nxp,lcd-8080.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,lcd-8080"
8 GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel).
9 These pins are exposed on a 32 pin connector. The pins have the
12 Pin Number Usage
24 12 LCD 8080 interface D/C pin
25 13 LCD 8080 interface CS pin
26 14 LCD 8080 interface WR pin
27 15 LCD 8080 interface RD pin
28 16 LCD TE(tearing effect) pin
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | nordic,nrf-qdec.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nordic,nrf-qdec"
8 include: [sensor-device.yaml, pinctrl-device.yaml]
17 pinctrl-0:
20 pinctrl-names:
23 enable-pin:
26 The enable pin to use, to enable a connected QDEC device
28 For pins P0.0 through P0.31, use the pin number. For example,
29 to use P0.16 for the A pin, set:
31 enable-pin = <16>;
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| D | st,iis328dq-common.yaml | 3 # SPDX-License-Identifier: Apache-2.0
5 include: sensor-device.yaml
8 int1-gpios:
9 type: phandle-array
11 INT_1 pin
13 This pin defaults to active high when produced by the sensor. The property value should ensure
16 int2-gpios:
17 type: phandle-array
19 INT_2 pin
21 This pin defaults to active high when produced by the sensor. The property value should ensure
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| D | nxp,fxls8974-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: FXLS8974 3-axis accelerometer sensor
6 include: sensor-device.yaml
9 reset-gpios:
10 type: phandle-array
12 RST pin
13 This pin defaults to active high when consumed by the sensor.
17 int1-gpios:
18 type: phandle-array
20 INT1 pin
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_numicro.c | 4 * SPDX-License-Identifier: Apache-2.0
16 #include <zephyr/dt-bindings/gpio/numicro-gpio.h>
19 #define MODE_PIN_SHIFT(pin) ((pin) * 2) argument
20 #define MODE_MASK(pin) (3 << MODE_PIN_SHIFT(pin)) argument
21 #define DINOFF_PIN_SHIFT(pin) ((pin) + 16) argument
22 #define DINOFF_MASK(pin) (1 << DINOFF_PIN_SHIFT(pin)) argument
23 #define PUSEL_PIN_SHIFT(pin) ((pin) * 2) argument
24 #define PUSEL_MASK(pin) (3 << PUSEL_PIN_SHIFT(pin)) argument
50 gpio_pin_t pin, gpio_flags_t flags) in gpio_numicro_configure() argument
52 const struct gpio_numicro_config *cfg = dev->config; in gpio_numicro_configure()
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| D | gpio_mcp23xxx.c | 5 * SPDX-License-Identifier: Apache-2.0
9 * @file Driver for MPC23xxx I2C/SPI-based GPIO driver.
42 const struct mcp23xxx_config *config = dev->config; in read_port_regs()
44 if (config->ngpios == 16U) { in read_port_regs()
48 return config->read_fn(dev, reg, buf); in read_port_regs()
65 const struct mcp23xxx_config *config = dev->config; in write_port_regs()
67 if (config->ngpios == 16U) { in write_port_regs()
71 return config->write_fn(dev, reg, value); in write_port_regs()
77 * IOCON is the only register that is not 16 bits wide on 16-pin devices; instead, it is mirrored in
78 * two adjacent memory locations. Because the underlying `write_fn` always does a 16-bit write for
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| D | wch_gpio_ch32v00x.c | 4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/dt-bindings/gpio/gpio.h>
28 static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) in gpio_ch32v00x_configure() argument
30 const struct gpio_ch32v00x_config *config = dev->config; in gpio_ch32v00x_configure()
31 GPIO_TypeDef *regs = config->regs; in gpio_ch32v00x_configure()
38 bshr = 1 << pin; in gpio_ch32v00x_configure()
40 bshr = 1 << (16 + pin); in gpio_ch32v00x_configure()
45 bshr = 1 << pin; in gpio_ch32v00x_configure()
48 bshr = 1 << (16 + pin); in gpio_ch32v00x_configure()
56 regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin)); in gpio_ch32v00x_configure()
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,flexio-pwm.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 The two PWM modes supported by flexio are chosen based on the selected polarity -
7 Dual 8-bit counters PWM mode and Dual 8-bit counters PWM Low mode.
9 compatible: "nxp,flexio-pwm"
11 include: [pwm-controller.yaml, pinctrl-device.yaml, base.yaml]
14 pinctrl-0:
17 pinctrl-names:
20 "#pwm-cells":
23 pwm-cells:
24 - channel
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| D | silabs,gecko-pwm.yaml | 3 compatible: "silabs,gecko-pwm"
5 include: [pwm-controller.yaml, base.yaml]
8 pin-location:
11 description: pwm pin configuration defined as <location port pin>
18 - 1
19 - 2
20 - 4
21 - 8
22 - 16
23 - 32
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| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | sifive,pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 value of IOF_EN/IOF_SEL registers to control pin settings.
9 Device pin configuration should be placed in the child nodes of this node.
10 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
12 - SIFIVE_PINMUX_IOF0
13 - SIFIVE_PINMUX_IOF1
15 For example, setting pins 16 and 17 both to IOF0 would look like this:
17 #include <dt-bindings/pinctrl/sifive-pinctrl.h>
21 pinmux = <16 SIFIVE_PINMUX_IOF0>;
36 child-binding:
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
22 description: Remaps the PA11 pin to operate as PA9 pin.
25 remap-pa12:
27 description: Remaps the PA12 pin to operate as PA10 pin.
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| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8XXX2 pin controller function node
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | renesas-rzt2m-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
10 #define RZT2M_PINMUX(port, pin, func) ((port << 16) | (pin << 8) | func) argument
12 #define UART0TX_P16_5 RZT2M_PINMUX(16, 5, 1)
13 #define UART0RX_P16_6 RZT2M_PINMUX(16, 6, 2)
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| D | gecko-pinctrl-s1.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
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| /Zephyr-latest/boards/shields/x_nucleo_eeprma2/ |
| D | x_nucleo_eeprma2.overlay | 4 * SPDX-License-Identifier: Apache-2.0
12 eeprom-0 = &eeprom0_x_nucleo_eeprma2;
13 eeprom-1 = &eeprom4_x_nucleo_eeprma2;
19 clock-frequency = <I2C_BITRATE_FAST>;
22 /* M24C02-FMC6TG aka U1 (2 kbit eeprom in DFN8 package) */
26 pagesize = <16>;
27 address-width = <8>;
30 /* if solder-bridge closed: arduino A1 pin on CN8 can wp */
31 /* wp-gpios = <&arduino_header 1 GPIO_ACTIVE_LOW>; */
35 /* M24256-DFDW6TP aka U2 (256 kbit eeprom in TSSOP package) */
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| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.spiram | 2 # SPDX-License-Identifier: Apache-2.0
7 bool "Support for external, SPI-connected RAM"
58 bool "ESP-PSRAM16 or APS1604"
62 bool "ESP-PSRAM32 or IS25WP032"
66 bool "ESP-PSRAM64, LY68L6400 or APS6408"
134 bool "Move Read-Only Data in Flash to PSRAM"
148 Enable MSPI Error-Correcting Code function when accessing SPIRAM.
149 If enabled, 1/16 of the SPI RAM total size will be reserved for error-correcting code.
153 menu "PSRAM clock and cs IO for ESP32-DOWD"
161 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
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| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | gd32f450i_eval.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 /* unplug camera from JP27 and bridge D0-D1 (pins 16 and 15) */
11 out-gpios = <&gpioc 6 0>; /* DCI D0 (JP27 pin 16)*/
12 in-gpios = <&gpioc 7 0>; /* DCI D1 (JP27 pin 15) */
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| /Zephyr-latest/soc/xlnx/zynq7000/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
89 #define MIO_PIN_SPECIAL_MASK_SDIO0_CD GENMASK(21, 16)
90 #define MIO_PIN_SPECIAL_SHIFT_SDIO0_CD 16
99 #define MIO_PIN_SPECIAL_MASK_SDIO1_CD GENMASK(21, 16)
100 #define MIO_PIN_SPECIAL_SHIFT_SDIO1_CD 16
107 /* MIO pin numbers */
124 #define MIO16 16
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
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| /Zephyr-latest/tests/drivers/i2c/i2c_target_api/boards/ |
| D | nucleo_h563zi.overlay | 3 * SPDX-License-Identifier: Apache-2.0
9 * Pin Hdr Pin Hdr
13 * Short Pin PB9 to PB11, and PB8 to PB10, for the test to pass.
17 pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
18 pinctrl-names = "default";
21 compatible = "zephyr,i2c-target-eeprom";
23 address-width = <16>;
29 pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
30 pinctrl-names = "default";
33 compatible = "zephyr,i2c-target-eeprom";
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| D | nucleo_l476rg.overlay | 3 * SPDX-License-Identifier: Apache-2.0
9 * Pin Hdr Pin Hdr
18 compatible = "zephyr,i2c-target-eeprom";
20 address-width = <16>;
27 compatible = "zephyr,i2c-target-eeprom";
29 address-width = <16>;
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| /Zephyr-latest/samples/drivers/adc/adc_dt/boards/ |
| D | lpcxpresso55s69_lpc55s69_cpu0.overlay | 2 * SPDX-License-Identifier: Apache-2.0
4 * Copyright 2022-2024 NXP
7 #include <zephyr/dt-bindings/adc/mcux-lpadc.h>
11 io-channels = <&adc0 0 &adc0 1 &adc0 2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 * - Connect VREFN_TARGET to GND, and VREFP_TARGET to 3v3
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)
25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)
27 * - Connect LPADC0 CH4A signal to voltage between 0~3.3V (P17 pin 19)
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| /Zephyr-latest/soc/ite/ec/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
15 * @brief ITE IT8XXX2 pin type.
21 * Pin configuration
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
23 * GPIO group pinctrl pins (include KSO[17:16]) support impedance,
24 * pull-up/down, voltage selection, input.
27 /* GPIO pin */
28 uint8_t pin; member
36 * @brief PIN configuration bitfield.
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