| /Zephyr-latest/boards/microchip/mec172xmodular_assy6930/support/ |
| D | spi_cfg_128MBit.txt | 5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
10 BoardID = 0x316
12 [IMAGE "0"]
13 ImageLocation = 0x2000
18 SpiSignalControl = 0x00
20 ImageRevision = 0x56
21 FwOffset = 0
22 FwLoadAddress = 0xC0000
[all …]
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| D | spi_cfg.txt | 5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
14 BoardID = 0
16 [IMAGE "0"]
17 ImageLocation = 0x1000
22 SpiSignalControl = 0x00
24 ImageRevision = 0x56
25 FwOffset = 0
26 FwLoadAddress = 0xC0000
[all …]
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| D | spi_cfg_4MBit.txt | 5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
14 BoardID = 0
16 [IMAGE "0"]
17 ImageLocation = 0x100
22 SpiSignalControl = 0x00
24 ImageRevision = 0x56
25 FwOffset = 0
26 FwLoadAddress = 0xC0000
[all …]
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| /Zephyr-latest/drivers/display/ |
| D | display_ist3931.h | 9 #define IST3931_CMD_NOP 0xe3
10 #define IST3931_CMD_IST_COMMAND_ENTRY 0x88
11 #define IST3931_CMD_EXIT_ENTRY 0xe3
12 #define IST3931_CMD_IST_COM_MAPPING 0x60
13 #define IST3931_CMD_POWER_CONTROL 0x2c
14 #define IST3931_CMD_BIAS 0x30
15 #define IST3931_CMD_CT 0xb1
16 #define IST3931_CMD_FRAME_CONTROL 0xb2
17 #define IST3931_CMD_SET_AX_ADD 0xc0
18 #define IST3931_CMD_SET_AY_ADD_LSB 0x00
[all …]
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| /Zephyr-latest/boards/microchip/mec172xevb_assy6906/support/ |
| D | spi_cfg.txt | 5 FlshmapAddr = 0
8 TagAddr0 = 0
9 TagAddr1 = 0
14 BoardID = 0
16 [IMAGE "0"]
17 ImageLocation = 0x2000
22 SpiSignalControl = 0x00
24 ImageRevision = 0x56
25 FwOffset = 0
26 FwLoadAddress = 0xC0000
[all …]
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| /Zephyr-latest/subsys/fb/ |
| D | cfb_fonts.c | 20 0x00, 0x00,
21 0x00, 0x00,
22 0x00, 0x00,
23 0x00, 0x00,
24 0x00, 0x00,
25 0x00, 0x00,
26 0x00, 0x00,
27 0x00, 0x00,
28 0x00, 0x00,
29 0x00, 0x00,
[all …]
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc11u6x.dtsi | 14 #size-cells = <0>;
16 cpu0: cpu@0 {
18 reg = <0>;
28 reg = <0x20000000 0x800>;
34 reg = <0x20004000 0x800>;
39 flash0:flash@0 {
56 reg = <0x40044000 0x150>;
59 ranges = <0x0 0x40044000 0x150>;
64 pio0: pio0@0 {
66 reg = <0x0 0x60>;
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/reset/ |
| D | stm32h5_reset.h | 13 #define STM32_RESET_BUS_AHB1 0x60
14 #define STM32_RESET_BUS_AHB2 0x64
15 #define STM32_RESET_BUS_AHB4 0x6C
16 #define STM32_RESET_BUS_APB1L 0x74
17 #define STM32_RESET_BUS_APB1H 0x78
18 #define STM32_RESET_BUS_APB2 0x7C
19 #define STM32_RESET_BUS_APB3 0x80
|
| D | stm32u5_reset.h | 13 #define STM32_RESET_BUS_AHB1 0x60
14 #define STM32_RESET_BUS_AHB2L 0x64
15 #define STM32_RESET_BUS_AHB2H 0x68
16 #define STM32_RESET_BUS_AHB3 0x6C
17 #define STM32_RESET_BUS_APB1L 0x74
18 #define STM32_RESET_BUS_APB1H 0x78
19 #define STM32_RESET_BUS_APB2 0x7C
20 #define STM32_RESET_BUS_APB3 0x80
|
| D | stm32wba_reset.h | 13 #define STM32_RESET_BUS_AHB1 0x60
14 #define STM32_RESET_BUS_AHB2 0x64
15 #define STM32_RESET_BUS_AHB4 0x6C
16 #define STM32_RESET_BUS_AHB5 0x70
17 #define STM32_RESET_BUS_APB1L 0x74
18 #define STM32_RESET_BUS_APB1H 0x78
19 #define STM32_RESET_BUS_APB2 0x7C
20 #define STM32_RESET_BUS_APB7 0x80
|
| /Zephyr-latest/tests/drivers/gpio/gpio_basic_api/boards/ |
| D | nrf54h20dk_nrf54h20_common.dtsi | 6 out-gpios = <&gpio0 6 0>;
7 in-gpios = <&gpio0 7 0>;
13 sense-edge-mask = <0x60>;
18 owned-channels = < 0 1 >;
|
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32wb0_clock.h | 22 #define STM32_CLOCK_BUS_AHB0 0x50
23 #define STM32_CLOCK_BUS_APB0 0x54
24 #define STM32_CLOCK_BUS_APB1 0x58
25 #define STM32_CLOCK_BUS_APB2 0x60
30 #define STM32_CLOCK_REG_MASK (0xFFFFU)
31 #define STM32_CLOCK_REG_SHIFT (0U)
32 #define STM32_CLOCK_SHIFT_MASK (0x3FU)
34 #define STM32_CLOCK_MASK_MASK (0x1FU)
47 * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ]
48 * @note 'shift' range: 0~63 [ 16 : 21 ]
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/led/ |
| D | seagate_legend_b1414.h | 17 #define ZERO_FRAME 0x60
18 #define ONE_FRAME 0x7C
|
| /Zephyr-latest/tests/kernel/fpu_sharing/generic/src/ |
| D | float_regs_sparc.h | 16 "ldd [%0 + 0x00], %%f0\n" in _load_all_float_registers()
17 "ldd [%0 + 0x08], %%f2\n" in _load_all_float_registers()
18 "ldd [%0 + 0x10], %%f4\n" in _load_all_float_registers()
19 "ldd [%0 + 0x18], %%f6\n" in _load_all_float_registers()
20 "ldd [%0 + 0x20], %%f8\n" in _load_all_float_registers()
21 "ldd [%0 + 0x28], %%f10\n" in _load_all_float_registers()
22 "ldd [%0 + 0x30], %%f12\n" in _load_all_float_registers()
23 "ldd [%0 + 0x38], %%f14\n" in _load_all_float_registers()
24 "ldd [%0 + 0x40], %%f16\n" in _load_all_float_registers()
25 "ldd [%0 + 0x48], %%f18\n" in _load_all_float_registers()
[all …]
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| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,lsm9ds1.yaml | 17 lsm9ds1: lsm9ds1@0 {
32 default: 0
36 - 0 # LSM9DS1_DT_FS_2G (0.061 mg/LSB)
41 enum: [0, 1, 2, 3]
45 default: 0
49 - 0 # LSM9DS1_DT_FS_245DPS (8.75 mdps/LSB)
53 enum: [0, 1, 3]
57 default: 0
63 - 0x00 # LSM9DS1_IMU_OFF
64 - 0x10 # LSM9DS1_GY_OFF_XL_10Hz
[all …]
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| /Zephyr-latest/tests/net/6lo/src/ |
| D | main.c | 36 #define DEBUG 0
49 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
50 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
53 { 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
54 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
57 { 0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
58 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa }
61 { 0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
62 0x00, 0x00, 0x00, 0xff, 0xfe, 0x00, 0x00, 0xbb }
64 { 0xfe, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
[all …]
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| /Zephyr-latest/samples/drivers/led/led_strip/ |
| D | f070rb-bindings.h | 14 * 0 bit: 300 ns high and 900 ns low.
23 #define B1414_ZERO_FRAME 0x60
24 #define B1414_ONE_FRAME 0x7C
|
| /Zephyr-latest/drivers/gnss/gnss_u_blox_protocol/ |
| D | gnss_u_blox_protocol_defines.h | 15 UBX_GNSS_ID_GPS = 0,
25 UBX_PORT_NUMBER_DDC = 0,
32 UBX_DYN_MODEL_PORTABLE = 0,
51 UBX_UTC_AUTOUTC = 0,
60 UBX_CLASS_NAV = 0x01,
61 UBX_CLASS_RXM = 0x02,
62 UBX_CLASS_INF = 0x04,
63 UBX_CLASS_ACK = 0x05,
64 UBX_CLASS_CFG = 0x06,
65 UBX_CLASS_UPD = 0x09,
[all …]
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| /Zephyr-latest/samples/sensor/vcnl4040/boards/ |
| D | adafruit_feather_stm32f405.overlay | 10 reg = <0x60>;
|
| /Zephyr-latest/include/zephyr/dt-bindings/sensor/ |
| D | lsm9ds1.h | 11 #define LSM9DS1_DT_FS_2G 0
16 #define LSM9DS1_DT_FS_245DPS 0
20 #define LSM9DS1_IMU_OFF 0x00
21 #define LSM9DS1_GY_OFF_XL_10Hz 0x10
22 #define LSM9DS1_GY_OFF_XL_50Hz 0x20
23 #define LSM9DS1_GY_OFF_XL_119Hz 0x30
24 #define LSM9DS1_GY_OFF_XL_238Hz 0x40
25 #define LSM9DS1_GY_OFF_XL_476Hz 0x50
26 #define LSM9DS1_GY_OFF_XL_952Hz 0x60
27 #define LSM9DS1_XL_OFF_GY_14Hz9 0x01
[all …]
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| D | it8xxx2_vcmp.h | 14 #define VCMP_CHANNEL_0 0
29 #define IT8XXX2_VCMP_SCAN_PERIOD_100US 0x10
30 #define IT8XXX2_VCMP_SCAN_PERIOD_200US 0x20
31 #define IT8XXX2_VCMP_SCAN_PERIOD_400US 0x30
32 #define IT8XXX2_VCMP_SCAN_PERIOD_600US 0x40
33 #define IT8XXX2_VCMP_SCAN_PERIOD_800US 0x50
34 #define IT8XXX2_VCMP_SCAN_PERIOD_1MS 0x60
35 #define IT8XXX2_VCMP_SCAN_PERIOD_1_5MS 0x70
36 #define IT8XXX2_VCMP_SCAN_PERIOD_2MS 0x80
37 #define IT8XXX2_VCMP_SCAN_PERIOD_2_5MS 0x90
[all …]
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| /Zephyr-latest/soc/renesas/ra/ra2a1/ |
| D | sections.ld | 22 . = __OPTION_SETTING_OFS_Start + 0x04;
24 . = __OPTION_SETTING_OFS_Start + 0x10;
27 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
38 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
48 . = __OPTION_SETTING_NS_Start + 0x04;
50 . = __OPTION_SETTING_NS_Start + 0x10;
52 . = __OPTION_SETTING_NS_Start + 0x40;
54 . = __OPTION_SETTING_NS_Start + 0x44;
56 . = __OPTION_SETTING_NS_Start + 0x48;
58 . = __OPTION_SETTING_NS_Start + 0x4C;
[all …]
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| /Zephyr-latest/soc/renesas/ra/ra4m1/ |
| D | sections.ld | 22 . = __OPTION_SETTING_OFS_Start + 0x04;
24 . = __OPTION_SETTING_OFS_Start + 0x10;
27 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
38 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
48 . = __OPTION_SETTING_NS_Start + 0x04;
50 . = __OPTION_SETTING_NS_Start + 0x10;
52 . = __OPTION_SETTING_NS_Start + 0x40;
54 . = __OPTION_SETTING_NS_Start + 0x44;
56 . = __OPTION_SETTING_NS_Start + 0x48;
58 . = __OPTION_SETTING_NS_Start + 0x4C;
[all …]
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| /Zephyr-latest/boards/snps/nsim/arc_classic/support/ |
| D | nsim_hs5x.props | 2 nsim_isa_core=0
3 arcver=0x60
5 nsim_isa_uarch_rev_major=0
6 nsim_isa_uarch_rev_minor=0
10 nsim_isa_big_endian=0
11 nsim_isa_lpc_size=0
19 nsim_isa_shift_option=0
21 nsim_isa_timer_0_int_level=0
23 nsim_isa_timer_1_int_level=0
47 nsim_isa_intvbase_preset=0x0
[all …]
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_dw_registers.h | 15 #define SWPORTA_DR 0x00
16 #define SWPORTA_DDR 0x04
17 #define SWPORTA_CTL 0x08
18 #define SWPORTB_DR 0x0c
19 #define SWPORTB_DDR 0x10
20 #define SWPORTB_CTL 0x14
21 #define SWPORTC_DR 0x18
22 #define SWPORTC_DDR 0x1c
23 #define SWPORTC_CTL 0x20
24 #define SWPORTD_DR 0x24
[all …]
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