Lines Matching +full:0 +full:x60
22 #define STM32_CLOCK_BUS_AHB0 0x50
23 #define STM32_CLOCK_BUS_APB0 0x54
24 #define STM32_CLOCK_BUS_APB1 0x58
25 #define STM32_CLOCK_BUS_APB2 0x60
30 #define STM32_CLOCK_REG_MASK (0xFFFFU)
31 #define STM32_CLOCK_REG_SHIFT (0U)
32 #define STM32_CLOCK_SHIFT_MASK (0x3FU)
34 #define STM32_CLOCK_MASK_MASK (0x1FU)
47 * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ]
48 * @note 'shift' range: 0~63 [ 16 : 21 ]
49 * @note 'mask' range: 0x00~0x1F [ 22 : 26 ]
50 * @note 'val' range: 0x00~0x1F [ 27 : 31 ]
59 #define CFGR_REG 0x08
62 #define APB2ENR_REG 0x60
67 /* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */