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/Zephyr-latest/boards/madmachine/mm_feather/
Dmmfeather_sdram_ini_dcd.c20 0xD2,
22 0x04, 0x30,
24 0x41,
26 0xCC, 0x03, 0xAC, 0x04,
28 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
30 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
32 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
34 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
36 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
38 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
[all …]
/Zephyr-latest/boards/madmachine/mm_swiftio/
Dmmswiftio_sdram_ini_dcd.c20 0xD2,
22 0x04, 0x30,
24 0x41,
26 0xCC, 0x03, 0xAC, 0x04,
28 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
30 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
32 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
34 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
36 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
38 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h11 * g = bits[0:4], GIRQ number in [8, 26]
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
20 (((g) & 0x1f) + (((gb) & 0x1f) << 8) + (((na) & 0xff) << 16) + \
21 (((nd) & 0xff) << 24))
24 #define MCHP_XEC_ECIA_GIRQ(e) ((e) & 0x1f)
25 #define MCHP_XEC_ECIA_GIRQ_POS(e) (((e) >> 8) & 0x1f)
26 #define MCHP_XEC_ECIA_NVIC_AGGR(e) (((e) >> 16) & 0xff)
27 #define MCHP_XEC_ECIA_NVIC_DIRECT(e) (((e) >> 24) & 0xff)
/Zephyr-latest/drivers/gpio/
Dgpio_max149x6.h11 #define MAX149x6_READ 0
14 #define MAX149X6_GET_BIT(val, i) (0x1 & ((val) >> (i)))
32 uint8_t crc5_start = 0x1f; in max149x6_crc()
33 uint8_t crc5_poly = 0x15; in max149x6_crc()
35 uint8_t extra_byte = 0x00; in max149x6_crc()
46 for (i = (encode) ? 0 : 2; i < 8; i++) { in max149x6_crc()
47 data_bit = (data[0] >> (7 - i)) & 0x01; in max149x6_crc()
48 result_bit = (crc5_result & 0x10) >> 4; in max149x6_crc()
50 crc5_result = crc5_poly ^ ((crc5_result << 1) & 0x1f); in max149x6_crc()
52 crc5_result = (crc5_result << 1) & 0x1f; in max149x6_crc()
[all …]
Dgpio_grgpio.h10 uint32_t data; /* 0x00 I/O port data register */
11 uint32_t output; /* 0x04 I/O port output register */
12 uint32_t dir; /* 0x08 I/O port direction register */
13 uint32_t imask; /* 0x0C Interrupt mask register */
14 uint32_t ipol; /* 0x10 Interrupt polarity register */
15 uint32_t iedge; /* 0x14 Interrupt edge register */
16 uint32_t bypass; /* 0x18 Bypass register */
17 uint32_t cap; /* 0x1C Capability register */
18 uint32_t irqmap[4]; /* 0x20 - 0x2C Interrupt map registers */
19 uint32_t res_30; /* 0x30 Reserved */
[all …]
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dprci.h11 #define PRCI_BASE_ADDR 0x10008000UL
18 #define PRCI_HFROSCCFG (0x0000)
19 #define PRCI_HFXOSCCFG (0x0004)
20 #define PRCI_PLLCFG (0x0008)
21 #define PRCI_PLLDIV (0x000C)
22 #define PRCI_PROCMONCFG (0x00F0)
25 #define ROSC_DIV(x) (((x) & 0x2F) << 0)
26 #define ROSC_TRIM(x) (((x) & 0x1F) << 16)
27 #define ROSC_EN(x) (((x) & 0x1) << 30)
28 #define ROSC_RDY(x) (((x) & 0x1) << 31)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h10 #define STM32_SRC_SYSCLK 0x001
12 #define STM32_SRC_LSE 0x002
13 #define STM32_SRC_LSI 0x003
16 #define NO_SEL 0xFF
24 #define STM32_MCO_CFGR_REG_MASK 0xFFFFU
25 #define STM32_MCO_CFGR_REG_SHIFT 0U
26 #define STM32_MCO_CFGR_SHIFT_MASK 0x3FU
28 #define STM32_MCO_CFGR_MASK_MASK 0x1FU
30 #define STM32_MCO_CFGR_VAL_MASK 0x1FU
39 * @param val Clock configuration field value (0~0x1F)
[all …]
Dstm32wb0_clock.h22 #define STM32_CLOCK_BUS_AHB0 0x50
23 #define STM32_CLOCK_BUS_APB0 0x54
24 #define STM32_CLOCK_BUS_APB1 0x58
25 #define STM32_CLOCK_BUS_APB2 0x60
30 #define STM32_CLOCK_REG_MASK (0xFFFFU)
31 #define STM32_CLOCK_REG_SHIFT (0U)
32 #define STM32_CLOCK_SHIFT_MASK (0x3FU)
34 #define STM32_CLOCK_MASK_MASK (0x1FU)
47 * @note 'reg' range: 0x0~0xFFFF [ 00 : 15 ]
48 * @note 'shift' range: 0~63 [ 16 : 21 ]
[all …]
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_pmc.c27 PMC->PMC_PCER1 = BIT(id & 0x1F); in soc_pmc_peripheral_enable()
44 PMC->PMC_PCDR1 = BIT(id & 0x1F); in soc_pmc_peripheral_disable()
58 return (PMC->PMC_PCSR0 & BIT(id)) != 0; in soc_pmc_peripheral_is_enabled()
61 return (PMC->PMC_PCSR1 & BIT(id & 0x1F)) != 0; in soc_pmc_peripheral_is_enabled()
69 return 0; in soc_pmc_peripheral_is_enabled()
Dsoc_sam4l_pm.c25 0, /* CPU GRP */
40 uint32_t per_idx = id & 0x1F; in soc_pmc_peripheral_enable()
56 PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) | in soc_pmc_peripheral_enable()
66 uint32_t per_idx = id & 0x1F; in soc_pmc_peripheral_disable()
82 PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) | in soc_pmc_peripheral_disable()
92 uint32_t per_idx = id & 0x1F; in soc_pmc_peripheral_is_enabled()
97 return 0; in soc_pmc_peripheral_is_enabled()
103 return 0; in soc_pmc_peripheral_is_enabled()
108 return ((mask & (1U << per_idx)) > 0); in soc_pmc_peripheral_is_enabled()
118 PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) | in soc_pm_enable_pba_divmask()
/Zephyr-latest/include/zephyr/arch/common/
Dsys_bitops.h65 sys_set_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_set_bit()
71 sys_clear_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_clear_bit()
77 return sys_test_bit(addr + ((bit >> 5) << 2), bit & 0x1F); in sys_bitfield_test_bit()
/Zephyr-latest/soc/sensry/ganymed/sy1xx/common/
Dsoc.c18 #define SY1XX_ARCHI_ITC_MASK_OFFSET 0x0
19 #define SY1XX_ARCHI_ITC_MASK_SET_OFFSET 0x4
20 #define SY1XX_ARCHI_ITC_MASK_CLR_OFFSET 0x8
21 #define SY1XX_ARCHI_ITC_STATUS_OFFSET 0xc
22 #define SY1XX_ARCHI_ITC_STATUS_SET_OFFSET 0x10
23 #define SY1XX_ARCHI_ITC_STATUS_CLR_OFFSET 0x14
24 #define SY1XX_ARCHI_ITC_ACK_OFFSET 0x18
25 #define SY1XX_ARCHI_ITC_ACK_SET_OFFSET 0x1c
26 #define SY1XX_ARCHI_ITC_ACK_CLR_OFFSET 0x20
27 #define SY1XX_ARCHI_ITC_FIFO_OFFSET 0x24
[all …]
/Zephyr-latest/tests/drivers/interrupt_controller/intc_plic/src/
Dmain.c18 zassert_equal(0, local_irq_to_reg_index(0x1f)); in ZTEST()
19 zassert_equal(1, local_irq_to_reg_index(0x20)); in ZTEST()
20 zassert_equal(1, local_irq_to_reg_index(0x3f)); in ZTEST()
21 zassert_equal(2, local_irq_to_reg_index(0x40)); in ZTEST()
27 zassert_equal(0, local_irq_to_reg_offset(0x1f)); in ZTEST()
28 zassert_equal(4, local_irq_to_reg_offset(0x20)); in ZTEST()
29 zassert_equal(4, local_irq_to_reg_offset(0x3f)); in ZTEST()
30 zassert_equal(8, local_irq_to_reg_offset(0x40)); in ZTEST()
39 zassert_equal(plic_hart_contexts_0[0], 0); in ZTEST()
49 zassert_equal(plic_hart_contexts_0[0], 0); in ZTEST()
/Zephyr-latest/dts/arm64/broadcom/
Dbcm2712.dtsi13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
43 reg = <0x0 0x200000 0x80000>;
48 reg = <0x10 0x7fff9000 0x1000>,
49 <0x10 0x7fffa000 0x2000>;
57 reg = <0x10 0x7d517c00 0x40>;
60 #size-cells = <0>;
61 gio_aon: gpio@0 {
63 reg = <0>;
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_mci_io_mux.c55 mask = 0x3 << ((gpio_idx & 0xF) << 1); in configure_pin_props()
56 set = IOMUX_PAD_GET_PULL(pin_mux) << ((gpio_idx & 0xF) << 1); in configure_pin_props()
60 set = IOMUX_PAD_GET_SLEW(pin_mux) << ((gpio_idx & 0xF) << 1); in configure_pin_props()
64 mask = (0x1 << (gpio_idx & 0x1F)); in configure_pin_props()
65 set = (IOMUX_PAD_GET_SLEEP_FORCE_EN(pin_mux) << (gpio_idx & 0x1F)); in configure_pin_props()
67 set = (IOMUX_PAD_GET_SLEEP_FORCE_VAL(pin_mux) << (gpio_idx & 0x1F)); in configure_pin_props()
84 ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
86 ~(0x1 << IOMUX_GET_CTIMER_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
91 ~(0x1 << IOMUX_GET_SCTIMER_IN_CLR_OFFSET(gpio_setting)); in select_gpio_mode()
95 ~(0x1 << (IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(gpio_setting) + 16)); in select_gpio_mode()
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_rf2xx.h16 RF2XX_TRX_PHY_STATE_CMD_NOP = 0x00,
17 RF2XX_TRX_PHY_STATE_CMD_TX_START = 0x02,
18 RF2XX_TRX_PHY_STATE_CMD_FORCE_TRX_OFF = 0x03,
19 RF2XX_TRX_PHY_STATE_CMD_FORCE_PLL_ON = 0x04,
20 RF2XX_TRX_PHY_STATE_CMD_RX_ON = 0x06,
21 RF2XX_TRX_PHY_STATE_CMD_TRX_OFF = 0x08,
22 RF2XX_TRX_PHY_STATE_CMD_PLL_ON = 0x09,
23 RF2XX_TRX_PHY_STATE_CMD_PREP_DEEP_SLEEP = 0x10,
24 RF2XX_TRX_PHY_STATE_CMD_RX_AACK_ON = 0x16,
25 RF2XX_TRX_PHY_STATE_CMD_TX_ARET_ON = 0x19,
[all …]
/Zephyr-latest/subsys/fb/
Dcfb_fonts.c20 0x00, 0x00,
21 0x00, 0x00,
22 0x00, 0x00,
23 0x00, 0x00,
24 0x00, 0x00,
25 0x00, 0x00,
26 0x00, 0x00,
27 0x00, 0x00,
28 0x00, 0x00,
29 0x00, 0x00,
[all …]
/Zephyr-latest/tests/modules/uoscore/src/oscore_testvector_tests/
Doscore_test_vectors.h16 const uint8_t T1__MASTER_SECRET[16] = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,
17 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c,
18 0x0d, 0x0e, 0x0f, 0x10 };
24 const uint8_t T1__RECIPIENT_ID[1] = { 0x01 };
27 const uint8_t T1__MASTER_SALT[8] = { 0x9e, 0x7c, 0xa9, 0x22,
28 0x23, 0x78, 0x63, 0x40 };
37 const uint8_t T1__COAP_REQ[] = { 0x44, 0x01, 0x5d, 0x1f, 0x00, 0x00, 0x39, 0x74,
38 0x39, 0x6c, 0x6f, 0x63, 0x61, 0x6c, 0x68, 0x6f,
39 0x73, 0x74, 0x83, 0x74, 0x76, 0x31 };
43 const uint8_t T1__SENDER_KEY[] = { 0xf0, 0x91, 0x0e, 0xd7, 0x29, 0x5e,
[all …]
/Zephyr-latest/subsys/bluetooth/mesh/
Dsar_cfg.c20 net_buf_simple_add_u8(buf, (tx->seg_int_step & 0xf) | in bt_mesh_sar_tx_encode()
23 0xf) | (tx->unicast_retrans_int_step << 4)); in bt_mesh_sar_tx_encode()
24 net_buf_simple_add_u8(buf, (tx->unicast_retrans_int_inc & 0xf) | in bt_mesh_sar_tx_encode()
26 net_buf_simple_add_u8(buf, tx->multicast_retrans_int & 0xf); in bt_mesh_sar_tx_encode()
32 net_buf_simple_add_u8(buf, (rx->seg_thresh & 0x1f) | in bt_mesh_sar_rx_encode()
34 net_buf_simple_add_u8(buf, (rx->discard_timeout & 0xf) | in bt_mesh_sar_rx_encode()
35 ((rx->rx_seg_int_step & 0xf) << 4)); in bt_mesh_sar_rx_encode()
36 net_buf_simple_add_u8(buf, (rx->ack_retrans_count & 0x3)); in bt_mesh_sar_rx_encode()
45 tx->seg_int_step = (val & 0xf); in bt_mesh_sar_tx_decode()
48 tx->unicast_retrans_without_prog_count = (val & 0xf); in bt_mesh_sar_tx_decode()
[all …]
/Zephyr-latest/tests/bsim/bluetooth/host/att/retry_on_sec_err/
Dcommon_defs.h8 BT_UUID_DECLARE_128(0x1f, 0x5c, 0x31, 0x85, 0x05, 0xe8, 0x4d, 0x58, 0xb9, 0xf5, 0xae, \
9 0xf1, 0x7a, 0x88, 0xbe, 0x82)
11 BT_UUID_DECLARE_128(0x68, 0xb4, 0x35, 0x19, 0x01, 0x65, 0x4d, 0xdc, 0xb9, 0xf3, 0x91, \
12 0x0f, 0xf3, 0x18, 0x46, 0x7b)
/Zephyr-latest/include/zephyr/arch/x86/
Dcpuid.h14 #define CPUID_BASIC_INFO_1 0x01
15 #define CPUID_EXTENDED_FEATURES_LVL 0x07
16 #define CPUID_EXTENDED_TOPOLOGY_ENUMERATION 0x0B
17 #define CPUID_EXTENDED_TOPOLOGY_ENUMERATION_V2 0x1F
/Zephyr-latest/tests/bluetooth/host/cs/bt_le_cs_set_valid_chmap_bits/src/
Dmain.c27 uint8_t correct_chmap[10] = {0xFC, 0xFF, 0x7F, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F}; in ZTEST()
/Zephyr-latest/soc/sensry/ganymed/sy1xx/
DKconfig.defconfig25 # default cluster id 0x3e, core 0 (FC) => 0x3e0 == 992
50 default 0x1F
/Zephyr-latest/tests/bsim/bluetooth/host/att/read_fill_buf/
Dcommon_defs.h9 BT_UUID_DECLARE_128(0xdb, 0x1f, 0xe2, 0x52, 0xf3, 0xc6, 0x43, 0x66, 0xb3, 0x92, 0x5d, \
10 0xc6, 0xe7, 0xc9, 0x59, 0x9d)
14 BT_UUID_DECLARE_128(0x3f, 0xa4, 0x7f, 0x44, 0x2e, 0x2a, 0x43, 0x05, 0xab, 0x38, 0x07, \
15 0x8d, 0x16, 0xbf, 0x99, 0xf1)
/Zephyr-latest/drivers/flash/
Djesd216.c20 res->mode_clocks = (packed >> 5) & 0x07; in extract_instr()
21 res->wait_states = packed & 0x1F; in extract_instr()
37 rv = 0; in jesd216_bfp_read_support()
43 rv = 0; in jesd216_bfp_read_support()
47 rv = 0; in jesd216_bfp_read_support()
53 rv = extract_instr(dw4 >> 0, res); in jesd216_bfp_read_support()
67 if ((dw17 >> 24) != 0) { in jesd216_bfp_read_support()
83 rv = extract_instr(dw3 >> 0, res); in jesd216_bfp_read_support()
90 if ((uint8_t)(dw17 >> 8) != 0) { in jesd216_bfp_read_support()
91 rv = extract_instr(dw17 >> 0, res); in jesd216_bfp_read_support()
[all …]

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