Searched +full:0 +full:x10000 (Results 1 – 25 of 160) sorted by relevance
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| /Zephyr-Core-3.6.0/dts/arm/nxp/ |
| D | nxp_s32z27x_rtu1_r52.dtsi | 12 /delete-node/ cpu@0;
21 reg = <0x76a00000 0x10000>;
29 reg = <0x76a10000 0x10000>;
37 reg = <0x76820000 0x10000>;
45 reg = <0x76830000 0x10000>;
53 reg = <0x76800000 0x10000>;
61 reg = <0x76810000 0x10000>;
69 reg = <0x76a20000 0x10000>;
77 reg = <0x76a30000 0x10000>;
85 reg = <0x76940000 0x10000>;
[all …]
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| D | nxp_s32z27x_rtu0_r52.dtsi | 21 reg = <0x76200000 0x10000>;
29 reg = <0x76210000 0x10000>;
37 reg = <0x76020000 0x10000>;
45 reg = <0x76030000 0x10000>;
53 reg = <0x76000000 0x10000>;
61 reg = <0x76010000 0x10000>;
69 reg = <0x76220000 0x10000>;
77 reg = <0x76230000 0x10000>;
85 reg = <0x76140000 0x10000>;
93 reg = <0x76150000 0x10000>;
[all …]
|
| D | nxp_s32z27x_r52.dtsi | 15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
86 reg = <0x40030000 0x10000>,
87 <0x40200000 0x10000>,
88 <0x40210000 0x10000>,
89 <0x40220000 0x10000>,
90 <0x40260000 0x10000>,
91 <0x40270000 0x10000>,
92 <0x40830000 0x10000>,
[all …]
|
| D | nxp_imx7d_m4.dtsi | 16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
29 reg = <0x10000000 0xfff0000>;
35 reg = <0x80000000 0x60000000>;
40 reg = <0x1fff8000 DT_SIZE_K(32)>;
45 reg = <0x20000000 DT_SIZE_K(32)>;
50 reg = <0x00900000 DT_SIZE_K(128)>;
56 reg = <0x20200000 DT_SIZE_K(128)>;
61 reg = <0x20180000 DT_SIZE_K(32)>;
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/cypress/ |
| D | psoc6.dtsi | 16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
32 reg = <0x40250000 0x10000>;
40 reg = <0x10000000 DT_SIZE_K(384)>;
46 reg = <0x10060000 DT_SIZE_K(640)>;
53 reg = <0x08000000 DT_SIZE_K(140)>;
58 reg = <0x08023000 DT_SIZE_K(4)>;
64 reg = <0x08024000 DT_SIZE_K(112)>;
73 ranges = <0x40310000 0x40310000 0x2024>;
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm64/fvp/ |
| D | fvp-aemv8r.dtsi | 13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
56 #clock-cells = <0>;
64 reg = <0xaf000000 0x10000>,
65 <0xaf100000 0x200000>;
73 reg = <0x9c090000 0x10000>;
82 reg = <0x9c0a0000 0x10000>;
91 reg = <0x9c0b0000 0x10000>;
100 reg = <0x9c0c0000 0x10000>;
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/infineon/psoc6/psoc6_04/ |
| D | psoc6_04.dtsi | 13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x40000>;
41 reg = <0x14000000 0x0>;
49 reg = <0x8000000 0x20000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/infineon/psoc6/psoc6_03/ |
| D | psoc6_03.dtsi | 13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x80000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x40000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm64/rockchip/ |
| D | rk3399.dtsi | 17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0x0 0x0>;
27 reg = <0x0 0x1>;
32 reg = <0x0 0x2>;
37 reg = <0x0 0x3>;
42 reg = <0x0 0x100>;
47 reg = <0x0 0x101>;
54 reg = <0xfee00000 0x10000>, /* GICD */
55 <0xfef00000 0xc0000>, /* GICR */
[all …]
|
| D | rk3568.dtsi | 23 #size-cells = <0>;
29 reg = <0x000>;
36 reg = <0x100>;
43 reg = <0x200>;
51 reg = <0x300>;
61 reg = <0xfd400000 0x10000>, /* GICD */
62 <0xfd460000 0xc0000>; /* GICR */
82 reg = <0xfe660000 0x10000>;
|
| /Zephyr-Core-3.6.0/tests/drivers/build_all/i2c/boards/ |
| D | qemu_cortex_m3.overlay | 11 #size-cells = <0>;
12 reg = <0x88888888 0x10000>;
20 #size-cells = <0>;
21 reg = <0x88898888 0x10000>;
|
| /Zephyr-Core-3.6.0/dts/bindings/ospi/ |
| D | st,stm32-ospi.yaml | 9 pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
15 dmas = <&dma1 5 41 0x10000>;
34 pinctrl-0:
47 dmas = <&dma1 5 41 0x10000>;
51 - 5: channel number (0 to Max-Channel minus 1). From 0 to 15 on stm32u5x.
53 - 0x10000: channel configuration (only for srce/dest data size, priority)
60 0 is a correct value.
64 dmas = <&dma1 5 41 0x10000>;
94 Specifies which port of the OCTOSPI IO Manager is used for the IO[3:0] pins.
|
| /Zephyr-Core-3.6.0/dts/arm/infineon/psoc6/psoc6_02/ |
| D | psoc6_02.dtsi | 13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40240000 0x10000 >;
35 reg = <0x10000000 0x200000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x100000>;
55 reg = <0x40300000 0x20000>;
57 #size-cells = <0>;
61 reg = <0x40300000 0x4000>;
[all …]
|
| /Zephyr-Core-3.6.0/boards/arm/arty/dts/ |
| D | arty_a7_arm_designstart.dtsi | 43 gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
87 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
107 gpios = <&gpio0_2 0 GPIO_ACTIVE_HIGH>;
127 gpios = <&gpio1_2 0 GPIO_ACTIVE_HIGH>;
152 interrupts = <7 0>;
153 mux-gpios = <&daplink_gpio0 0 GPIO_ACTIVE_HIGH>;
160 reg = <0x40010000 0x10000>;
164 xlnx,all-inputs = <0x0>;
165 xlnx,all-outputs = <0x0>;
166 xlnx,dout-default = <0x0>;
[all …]
|
| /Zephyr-Core-3.6.0/dts/arm/infineon/psoc6/psoc6_01/ |
| D | psoc6_01.dtsi | 13 #size-cells = <0>;
15 cpu@0 {
18 reg = <0>;
29 reg = < 0x40250000 0x10000 >;
35 reg = <0x10000000 0x100000>;
41 reg = <0x14000000 0x8000>;
49 reg = <0x8000000 0x48000>;
55 reg = <0x40310000 0x20000>;
57 #size-cells = <0>;
62 reg = <0x40310000 0x4000>;
[all …]
|
| /Zephyr-Core-3.6.0/boards/arm/mimx8mp_phyboard_pollux/ |
| D | mimx8mp_phyboard_pollux.dts | 31 reg = <0x30860000 0x10000>;
33 clocks = <&ccm IMX_CCM_UART1_CLK 0x7c 24>;
34 pinctrl-0 = <&uart1_default>;
45 reg = <0x30880000 0x10000>;
47 clocks = <&ccm IMX_CCM_UART3_CLK 0x68 12>;
48 pinctrl-0 = <&uart3_default>;
62 pinctrl-0 = <&uart4_default>;
|
| /Zephyr-Core-3.6.0/dts/riscv/starfive/ |
| D | starfive_jh7100_beagle_v.dtsi | 18 #size-cells = <0>;
20 cpu@0 {
21 clock-frequency = <0>;
36 reg = <0>;
43 #address-cells = <0>;
50 clock-frequency = <0>;
72 #address-cells = <0>;
81 reg = <0x0 0x80000000 0x2 0x0>;
101 reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
107 reg = <0x0 0x1808000 0x0 0x8000>;
[all …]
|
| /Zephyr-Core-3.6.0/soc/xtensa/nxp_adsp/imx8ulp/include/ |
| D | memory.h | 9 #define IRAM_RESERVE_HEADER_SPACE 0x400
11 #define IRAM_BASE 0x21170000
12 #define IRAM_SIZE 0x10000
14 #define SDRAM0_BASE 0x1a000000
15 #define SDRAM0_SIZE 0x800000
17 #define SDRAM1_BASE 0x1a800000
18 #define SDRAM1_SIZE 0x800000
21 #define MEM_RESET_TEXT_SIZE 0x2e0
22 #define MEM_RESET_LIT_SIZE 0x120
28 #define MEM_VECBASE_LIT_SIZE 0x178
[all …]
|
| /Zephyr-Core-3.6.0/dts/xtensa/nxp/ |
| D | nxp_imx8m.dtsi | 14 #size-cells = <0>;
16 cpu0: cpu@0 {
19 reg = <0>;
22 #size-cells = <0>;
24 clic: interrupt-controller@0 {
26 reg = <0>;
36 reg = <0x92400000 DT_SIZE_K(512)>;
42 reg = <0x92c00000 DT_SIZE_K(512)>;
48 reg = <0x30380000 DT_SIZE_K(64)>;
54 reg = <0x30330000 DT_SIZE_K(64)>;
[all …]
|
| /Zephyr-Core-3.6.0/boards/arm64/xenvm/ |
| D | xenvm_gicv3.dts | 10 reg = <0x00 0x3001000 0x00 0x10000 0x00 0x3020000 0x00 0x1000000>;
|
| /Zephyr-Core-3.6.0/dts/arm/xilinx/ |
| D | zynqmp_rpu.dtsi | 12 #size-cells = <0>;
14 cpu@0 {
17 reg = <0>;
29 reg = <0xff310000 0x10000>;
36 remote-ipi-id = <0>;
37 reg = <0xff990200 0x20>,
38 <0xff990220 0x20>,
39 <0xff990040 0x20>,
40 <0xff990060 0x20>;
49 reg = <0xff990260 0x20>,
[all …]
|
| /Zephyr-Core-3.6.0/boards/arm/steval_fcu001v1/support/ |
| D | openocd.cfg | 5 set WORKAREASIZE 0x10000
|
| /Zephyr-Core-3.6.0/tests/subsys/settings/functional/fcb/boards/ |
| D | nrf52dk_nrf52832.overlay | 19 reg = <0x00070000 0x10000>;
|
| /Zephyr-Core-3.6.0/tests/drivers/build_all/watchdog/boards/ |
| D | qemu_cortex_m3.overlay | 10 reg = <0x88888888 0x10000>;
|
| /Zephyr-Core-3.6.0/tests/subsys/settings/fcb/boards/ |
| D | nrf52dk_nrf52832.overlay | 19 reg = <0x00070000 0x10000>;
|
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