1/* 2 * Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or 3 * an affiliate of Cypress Semiconductor Corporation 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8#include <mem.h> 9 10/ { 11 cpus { 12 #address-cells = <1>; 13 #size-cells = <0>; 14 15 cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-m0+"; 18 reg = <0>; 19 }; 20 cpu@1 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-m4f"; 23 reg = <1>; 24 }; 25 }; 26 27 flash-controller@40240000 { 28 compatible = "infineon,cat1-flash-controller"; 29 reg = < 0x40240000 0x10000 >; 30 #address-cells = <1>; 31 #size-cells = <1>; 32 33 flash0: flash@10000000 { 34 compatible = "soc-nv-flash"; 35 reg = <0x10000000 0x40000>; 36 write-block-size = <512>; 37 erase-block-size = <512>; 38 }; 39 flash1: flash@14000000 { 40 compatible = "soc-nv-flash"; 41 reg = <0x14000000 0x0>; 42 write-block-size = <512>; 43 erase-block-size = <512>; 44 }; 45 }; 46 47 sram0: memory@8000000 { 48 compatible = "mmio-sram"; 49 reg = <0x8000000 0x20000>; 50 }; 51 52 soc { 53 pinctrl: pinctrl@40300000 { 54 compatible = "infineon,cat1-pinctrl"; 55 reg = <0x40300000 0x20000>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 hsiom: hsiom@40300000 { 60 compatible = "infineon,cat1-hsiom"; 61 reg = <0x40300000 0x4000>; 62 interrupts = <15 6>, <16 6>; 63 status = "disabled"; 64 }; 65 66 gpio_prt0: gpio@40310000 { 67 compatible = "infineon,cat1-gpio"; 68 reg = <0x40310000 0x80>; 69 interrupts = <0 6>; 70 gpio-controller; 71 ngpios = <6>; 72 status = "disabled"; 73 #gpio-cells = <2>; 74 }; 75 gpio_prt1: gpio@40310080 { 76 compatible = "infineon,cat1-gpio"; 77 reg = <0x40310080 0x80>; 78 gpio-controller; 79 ngpios = <3>; 80 status = "disabled"; 81 #gpio-cells = <2>; 82 }; 83 gpio_prt2: gpio@40310100 { 84 compatible = "infineon,cat1-gpio"; 85 reg = <0x40310100 0x80>; 86 interrupts = <2 6>; 87 gpio-controller; 88 ngpios = <8>; 89 status = "disabled"; 90 #gpio-cells = <2>; 91 }; 92 gpio_prt3: gpio@40310180 { 93 compatible = "infineon,cat1-gpio"; 94 reg = <0x40310180 0x80>; 95 interrupts = <3 6>; 96 gpio-controller; 97 ngpios = <2>; 98 status = "disabled"; 99 #gpio-cells = <2>; 100 }; 101 gpio_prt5: gpio@40310280 { 102 compatible = "infineon,cat1-gpio"; 103 reg = <0x40310280 0x80>; 104 interrupts = <5 6>; 105 gpio-controller; 106 ngpios = <5>; 107 status = "disabled"; 108 #gpio-cells = <2>; 109 }; 110 gpio_prt6: gpio@40310300 { 111 compatible = "infineon,cat1-gpio"; 112 reg = <0x40310300 0x80>; 113 interrupts = <6 6>; 114 gpio-controller; 115 ngpios = <6>; 116 status = "disabled"; 117 #gpio-cells = <2>; 118 }; 119 gpio_prt7: gpio@40310380 { 120 compatible = "infineon,cat1-gpio"; 121 reg = <0x40310380 0x80>; 122 interrupts = <7 6>; 123 gpio-controller; 124 ngpios = <7>; 125 status = "disabled"; 126 #gpio-cells = <2>; 127 }; 128 gpio_prt8: gpio@40310400 { 129 compatible = "infineon,cat1-gpio"; 130 reg = <0x40310400 0x80>; 131 interrupts = <8 6>; 132 gpio-controller; 133 ngpios = <2>; 134 status = "disabled"; 135 #gpio-cells = <2>; 136 }; 137 gpio_prt9: gpio@40310480 { 138 compatible = "infineon,cat1-gpio"; 139 reg = <0x40310480 0x80>; 140 interrupts = <9 6>; 141 gpio-controller; 142 ngpios = <6>; 143 status = "disabled"; 144 #gpio-cells = <2>; 145 }; 146 gpio_prt10: gpio@40310500 { 147 compatible = "infineon,cat1-gpio"; 148 reg = <0x40310500 0x80>; 149 interrupts = <10 6>; 150 gpio-controller; 151 ngpios = <8>; 152 status = "disabled"; 153 #gpio-cells = <2>; 154 }; 155 gpio_prt11: gpio@40310580 { 156 compatible = "infineon,cat1-gpio"; 157 reg = <0x40310580 0x80>; 158 interrupts = <11 6>; 159 gpio-controller; 160 ngpios = <7>; 161 status = "disabled"; 162 #gpio-cells = <2>; 163 }; 164 gpio_prt12: gpio@40310600 { 165 compatible = "infineon,cat1-gpio"; 166 reg = <0x40310600 0x80>; 167 interrupts = <12 6>; 168 gpio-controller; 169 ngpios = <2>; 170 status = "disabled"; 171 #gpio-cells = <2>; 172 }; 173 gpio_prt14: gpio@40310700 { 174 compatible = "infineon,cat1-gpio"; 175 reg = <0x40310700 0x80>; 176 interrupts = <14 6>; 177 gpio-controller; 178 ngpios = <2>; 179 status = "disabled"; 180 #gpio-cells = <2>; 181 }; 182 }; 183 uid: device_uid@16000600 { 184 compatible = "infineon,cat1-uid"; 185 reg = <0x16000600 0xb>; 186 status = "disabled"; 187 }; 188 189 adc0: adc@409b0000 { 190 compatible = "infineon,cat1-adc"; 191 reg = <0x409b0000 0x10000>; 192 interrupts = <39 6>; 193 status = "disabled"; 194 }; 195 adc1: adc@409c0000 { 196 compatible = "infineon,cat1-adc"; 197 reg = <0x409c0000 0x10000>; 198 interrupts = <40 6>; 199 status = "disabled"; 200 }; 201 202 scb0: scb@40600000 { 203 compatible = "infineon,cat1-scb"; 204 reg = <0x40600000 0x10000>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 interrupts = <45 6>; 208 status = "disabled"; 209 }; 210 scb1: scb@40610000 { 211 compatible = "infineon,cat1-scb"; 212 reg = <0x40610000 0x10000>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 interrupts = <46 6>; 216 status = "disabled"; 217 }; 218 scb2: scb@40620000 { 219 compatible = "infineon,cat1-scb"; 220 reg = <0x40620000 0x10000>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 interrupts = <47 6>; 224 status = "disabled"; 225 }; 226 scb4: scb@40640000 { 227 compatible = "infineon,cat1-scb"; 228 reg = <0x40640000 0x10000>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <49 6>; 232 status = "disabled"; 233 }; 234 scb5: scb@40650000 { 235 compatible = "infineon,cat1-scb"; 236 reg = <0x40650000 0x10000>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 interrupts = <50 6>; 240 status = "disabled"; 241 }; 242 scb6: scb@40660000 { 243 compatible = "infineon,cat1-scb"; 244 reg = <0x40660000 0x10000>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 interrupts = <18 6>; 248 status = "disabled"; 249 }; 250 sdhc0: sdhc@40460000 { 251 compatible = "infineon,cat1-sdhc-sdio"; 252 reg = <0x40460000 0x2000>; 253 interrupts = <164 6>; 254 status = "disabled"; 255 }; 256 257 }; 258}; 259
