1/*
2 * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6#include <mem.h>
7#include <arm64/armv8-r.dtsi>
8#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	cpus {
12		#address-cells = <1>;
13		#size-cells = <0>;
14
15		cpu@0 {
16			device_type = "cpu";
17			compatible = "arm,cortex-r82";
18			reg = <0>;
19		};
20
21		cpu@1 {
22			device_type = "cpu";
23			compatible = "arm,cortex-r82";
24			reg = <1>;
25		};
26
27		cpu@2 {
28			device_type = "cpu";
29			compatible = "arm,cortex-r82";
30			reg = <2>;
31		};
32
33		cpu@3 {
34			device_type = "cpu";
35			compatible = "arm,cortex-r82";
36			reg = <3>;
37		};
38	};
39
40	timer {
41		compatible = "arm,armv8-timer";
42		interrupt-parent = <&gic>;
43		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
44			      IRQ_DEFAULT_PRIORITY>,
45			     <GIC_PPI 14 IRQ_TYPE_LEVEL
46			      IRQ_DEFAULT_PRIORITY>,
47			     <GIC_PPI 11 IRQ_TYPE_LEVEL
48			      IRQ_DEFAULT_PRIORITY>,
49			     <GIC_PPI 10 IRQ_TYPE_LEVEL
50			      IRQ_DEFAULT_PRIORITY>;
51	};
52
53	uartclk: apb-pclk {
54		compatible = "fixed-clock";
55		clock-frequency = <24000000>;
56		#clock-cells = <0>;
57	};
58
59	soc {
60		interrupt-parent = <&gic>;
61
62		gic: interrupt-controller@af000000 {
63			compatible = "arm,gic-v3", "arm,gic";
64			reg = <0xaf000000 0x10000>,
65			      <0xaf100000 0x200000>;
66			interrupt-controller;
67			#interrupt-cells = <4>;
68			status = "okay";
69		};
70
71		uart0: uart@9c090000 {
72			compatible = "arm,pl011";
73			reg = <0x9c090000 0x10000>;
74			status = "disabled";
75			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
76			interrupt-names = "irq_5";
77			clocks = <&uartclk>;
78		};
79
80		uart1: uart@9c0a0000 {
81			compatible = "arm,pl011";
82			reg = <0x9c0a0000 0x10000>;
83			status = "disabled";
84			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
85			interrupt-names = "irq_6";
86			clocks = <&uartclk>;
87		};
88
89		uart2: uart@9c0b0000 {
90			compatible = "arm,pl011";
91			reg = <0x9c0b0000 0x10000>;
92			status = "disabled";
93			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
94			interrupt-names = "irq_7";
95			clocks = <&uartclk>;
96		};
97
98		uart3: uart@9c0c0000 {
99			compatible = "arm,pl011";
100			reg = <0x9c0c0000 0x10000>;
101			status = "disabled";
102			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
103			interrupt-names = "irq_8";
104			clocks = <&uartclk>;
105		};
106
107		ethernet@9a000000 {
108			reg = <0x9a000000 0x1000>;
109
110			eth: ethernet {
111				compatible = "smsc,lan91c111";
112				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
113				status = "disabled";
114
115				phy-handle = <&phy>;
116			};
117
118			mdio: mdio {
119				compatible = "smsc,lan91c111-mdio";
120				status = "disabled";
121				#address-cells = <1>;
122				#size-cells = <0>;
123
124				phy: ethernet-phy@0 {
125					compatible = "ethernet-phy";
126					status = "disabled";
127					reg = <0>;
128				};
129			};
130		};
131	};
132};
133