1/*
2 * Copyright 2022 Huawei France Technologies SASU
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm64/armv8-a.dtsi>
8#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
9#include <mem.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	cpus {
16		#address-cells = <2>;
17		#size-cells = <0>;
18
19		cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-a53";
22			reg = <0x0 0x0>;
23		};
24		cpu@1 {
25			device_type = "cpu";
26			compatible = "arm,cortex-a53";
27			reg = <0x0 0x1>;
28		};
29		cpu@2 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a53";
32			reg = <0x0 0x2>;
33		};
34		cpu@3 {
35			device_type = "cpu";
36			compatible = "arm,cortex-a53";
37			reg = <0x0 0x3>;
38		};
39		cpu@4 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a72";
42			reg = <0x0 0x100>;
43		};
44		cpu@5 {
45			device_type = "cpu";
46			compatible = "arm,cortex-a72";
47			reg = <0x0 0x101>;
48		};
49	};
50
51	gic: interrupt-controller@fee00000  {
52		#address-cells = <1>;
53		compatible = "arm,gic-v3", "arm,gic";
54		reg = <0xfee00000 0x10000>, /* GICD */
55		      <0xfef00000 0xc0000>, /* GICR */
56		      <0xfff00000 0x10000>, /* GICC */
57		      <0xfff10000 0x10000>, /* GICH */
58		      <0xfff20000 0x10000>; /* GICV */
59		interrupt-controller;
60		#interrupt-cells = <4>;
61		status = "okay";
62	};
63
64	psci: psci {
65		compatible = "arm,psci-1.0";
66		method = "smc";
67	};
68
69	sram0: memory@10000000 {
70		reg = <0x10000000 DT_SIZE_M(128)>;
71	};
72
73	timer {
74		compatible = "arm,armv8-timer";
75		interrupt-parent = <&gic>;
76		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
77			      IRQ_DEFAULT_PRIORITY>,
78			     <GIC_PPI 14 IRQ_TYPE_LEVEL
79			      IRQ_DEFAULT_PRIORITY>,
80			     <GIC_PPI 11 IRQ_TYPE_LEVEL
81			      IRQ_DEFAULT_PRIORITY>,
82			     <GIC_PPI 10 IRQ_TYPE_LEVEL
83			      IRQ_DEFAULT_PRIORITY>;
84	};
85
86	uart2: serial@ff1a0000  {
87		compatible = "rockchip,rk3399-uart", "ns16550";
88		reg = <0xff1a0000 0x1000>;
89		interrupt-parent = <&gic>;
90		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
91		status = "disabled";
92		reg-shift = <2>;
93		clock-frequency = <350000000>;
94	};
95};
96