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/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-ospi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
9 mx25lm51245: ospi-nor-flash@70000000 {
10 compatible = "st,stm32-ospi-nor";
11 reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
12 data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
13 data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
18 compatible: "st,stm32-ospi-nor"
20 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
22 on-bus: ospi
[all …]
/Zephyr-latest/soc/espressif/esp32/
Dgdbstub.c4 * SPDX-License-Identifier: Apache-2.0
19 .start = 0x3F400000,
20 .end = 0x3FBFFFFF,
22 .alignment = 4,
26 .start = 0x3FF00000,
27 .end = 0x3FF7FFFF,
29 .alignment = 4,
33 .start = 0x3FF80000,
34 .end = 0x3FF81FFF,
36 .alignment = 4,
[all …]
/Zephyr-latest/dts/arm/infineon/cat1b/cyw20829/
Dcyw20829.dtsi5 * SPDX-License-Identifier: Apache-2.0
12 #address-cells = <1>;
13 #size-cells = <0>;
15 cpu@0 {
17 compatible = "arm,cortex-m33";
18 reg = <0>;
19 cpu-power-states = <&idle &suspend_to_ram>;
22 power-states {
24 compatible = "zephyr,power-state";
25 power-state-name = "suspend-to-idle";
[all …]
/Zephyr-latest/drivers/flash/
Dspi_nor.h2 * Copyright (c) 2018 Savoir-Faire Linux.
4 * SPDX-License-Identifier: Apache-2.0
15 #define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
19 #define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
20 #define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
21 #define SPI_NOR_CMD_WRSR2 0x31 /* Write status register 2 */
22 #define SPI_NOR_CMD_RDSR2 0x35 /* Read status register 2 */
23 #define SPI_NOR_CMD_RDSR3 0x15 /* Read status register 3 */
24 #define SPI_NOR_CMD_WRSR3 0x11 /* Write status register 3 */
25 #define SPI_NOR_CMD_READ 0x03 /* Read data */
[all …]
Dflash_mcux_flexspi_hyperflash.c5 * SPDX-License-Identifier: Apache-2.0
24 #if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
26 read-while-write hazards. This configuration is not recommended."
39 #define SPI_HYPERFLASH_SECTOR_SIZE (0x40000U)
42 #define HYPERFLASH_ERASE_VALUE (0xFF)
50 READ_DATA = 0,
53 WRITE_ENABLE = 4,
63 [4 * READ_DATA] =
64 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR, kFLEXSPI_8PAD, 0xA0,
65 kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x18),
[all …]
/Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
24 #define BT_UUID_SERVICE_A BT_UUID_DECLARE_16(0xa00a)
29 #define BT_UUID_VALUE_V1 BT_UUID_DECLARE_16(0xb001)
34 #define BT_UUID_VALUE_V2 BT_UUID_DECLARE_16(0xb002)
39 #define BT_UUID_VALUE_V3 BT_UUID_DECLARE_16(0xb003)
41 static uint8_t value_v1_value = 0x01;
44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
48 '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6',
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_rf2xx_regs.h1 /* ieee802154_rf2xx_regs.h - ATMEL RF2XX transceiver registers */
6 * SPDX-License-Identifier: Apache-2.0
12 /*- Definitions ------------------------------------------------------------*/
23 #define RX2XX_FRAME_TRAC_INDEX 4
27 #define RF2XX_RSSI_BPSK_20 -100
28 #define RF2XX_RSSI_BPSK_40 -99
29 #define RF2XX_RSSI_OQPSK_SIN_RC_100 -98
30 #define RF2XX_RSSI_OQPSK_SIN_250 -97
31 #define RF2XX_RSSI_OQPSK_RC_250 -97
33 /*- Types ------------------------------------------------------------------*/
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a779f0.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
13 #define PIN_SCIF_CLK RCAR_GP_PIN(0, 0)
14 #define PIN_HSCK0 RCAR_GP_PIN(0, 1)
15 #define PIN_HRX0 RCAR_GP_PIN(0, 2)
16 #define PIN_HTX0 RCAR_GP_PIN(0, 3)
17 #define PIN_HCTS0_N RCAR_GP_PIN(0, 4)
18 #define PIN_HRTS0_N RCAR_GP_PIN(0, 5)
19 #define PIN_RX0 RCAR_GP_PIN(0, 6)
[all …]
Dpinctrl-r8a77961.h3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
14 #define PIN_D0 RCAR_GP_PIN(0, 0)
15 #define PIN_D1 RCAR_GP_PIN(0, 1)
16 #define PIN_D2 RCAR_GP_PIN(0, 2)
17 #define PIN_D3 RCAR_GP_PIN(0, 3)
18 #define PIN_D4 RCAR_GP_PIN(0, 4)
19 #define PIN_D5 RCAR_GP_PIN(0, 5)
[all …]
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
13 #define PIN_D0 RCAR_GP_PIN(0, 0)
14 #define PIN_D1 RCAR_GP_PIN(0, 1)
15 #define PIN_D2 RCAR_GP_PIN(0, 2)
16 #define PIN_D3 RCAR_GP_PIN(0, 3)
17 #define PIN_D4 RCAR_GP_PIN(0, 4)
18 #define PIN_D5 RCAR_GP_PIN(0, 5)
19 #define PIN_D6 RCAR_GP_PIN(0, 6)
[all …]
/Zephyr-latest/dts/arm/infineon/cat3/xmc/
Dxmc4500_F100x1024-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
Dxmc4700_F144x2048-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h7 * SPDX-License-Identifier: Apache-2.0
15 * ---
17 * -2-
18 * 0| |6
19 * ---
20 * 4
23 #define CHAR_OFF (0)
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
12 /* MIWU table 0 */
14 wui_io80: wui0-1-0 {
15 miwus = <&miwu0 0 0>; /* GPIO80 */
17 wui_io81: wui0-1-1 {
18 miwus = <&miwu0 0 1>; /* GPIO81 */
20 wui_io82: wui0-1-2 {
21 miwus = <&miwu0 0 2>; /* GPIO82 */
[all …]
Dnpcx-lvol-ctrl-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 def-lvol-conf-list {
9 compatible = "nuvoton,npcx-lvolctrl-conf";
11 /* Low-Voltage IO Control 0 */
13 lvols = <&scfg 0 0>;
16 lvols = <&scfg 0 1>;
19 lvols = <&scfg 0 2>;
22 lvols = <&scfg 0 3>;
25 lvols = <&scfg 0 4>;
28 lvols = <&scfg 0 5>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dnumaker_m2l31x_reset.h4 * SPDX-License-Identifier: Apache-2.0
12 #define LPSCC_IPRST0_LPPDMA0RST_Pos 0
25 #define SYS_IPRST0_CHIPRST_Pos 0
29 #define SYS_IPRST0_USBHRST_Pos 4
37 #define SYS_IPRST1_TMR2RST_Pos 4
81 /*---------------------------------------------------------------------
83 *---------------------------------------------------------------------
86 #define NUMAKER_PDMA0_RST ((0UL<<24) | SYS_IPRST0_PDMA0RST_Pos)
87 #define NUMAKER_EBI_RST ((0UL<<24) | SYS_IPRST0_EBIRST_Pos)
88 #define NUMAKER_USBH_RST ((0UL<<24) | SYS_IPRST0_USBHRST_Pos)
[all …]
Dnumaker_m46x_reset.h4 * SPDX-License-Identifier: Apache-2.0
56 #define NUMAKER_SYS_IPRST1_TMR2RST_Pos (4)
106 #define NUMAKER_SYS_IPRST2_SC0RST_Pos (0)
114 #define NUMAKER_SYS_IPRST2_QSPI1RST_Pos (4)
154 #define NUMAKER_SYS_IPRST3_KPIRST_Pos (0)
180 /*---------------------------------------------------------------------
182 *---------------------------------------------------------------------
184 #define NUMAKER_PDMA0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_PDMA0RST_Pos)
185 #define NUMAKER_EBI_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_EBIRST_Pos)
186 #define NUMAKER_EMAC0_RST ((0UL << 24) | NUMAKER_SYS_IPRST0_EMAC0RST_Pos)
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/Zephyr-latest/subsys/net/ip/
Dnet_tc_mapping.h10 * SPDX-License-Identifier: Apache-2.0
19 * according to 802.1Q - table I-2.
23 * 0 (default) BE Best effort
26 * 4 VI Video, < 100 ms latency and jitter
36 #if defined(CONFIG_NET_TC_MAPPING_STRICT) && (NET_TC_COUNT > 0)
39 * implementations that do not support the credit-based shaper transmission
41 * Ref: 802.1Q - chapter 8.6.6 - table 8-4
45 static const uint8_t priority2tc_strict_1[] = {0, 0, 0, 0, 0, 0, 0, 0};
48 static const uint8_t priority2tc_strict_2[] = {0, 0, 0, 0, 1, 1, 1, 1};
51 static const uint8_t priority2tc_strict_3[] = {0, 0, 0, 0, 1, 1, 2, 2};
[all …]
/Zephyr-latest/tests/subsys/debug/coredump_threads/
Dtestcase.yaml2 # SPDX-License-Identifier: Apache-2.0
6 - coredump
10 - qemu_cortex_m3
20 - "E: #CD:BEGIN#"
21 - "E: #CD:5([aA])45([0-9a-fA-F]+)"
22 - "E: #CD:41([0-9a-fA-F]+)"
23 - "E: #CD:54([0-9a-fA-F]+)"
24 - "E: #CD:4([dD])([0-9a-fA-F]+)"
25 - "E: #CD:4([dD])([0-9a-fA-F]+)"
26 - "E: #CD:4([dD])([0-9a-fA-F]+)"
[all …]
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_b91.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \
30 * pin_mux: PORT_A[0-3]
[all …]
/Zephyr-latest/tests/drivers/coredump/coredump_api/
Dtestcase.yaml2 # SPDX-License-Identifier: Apache-2.0
6 - coredump
18 - "E: #CD:BEGIN#"
19 - "E: #CD:5([aA])45([0-9a-fA-F]+)"
20 - "E: #CD:4([dD])([0-9a-fA-F]+)"
21 - "E: #CD:4([dD])([0-9a-fA-F]+)"
22 - "E: #CD:4([dD])([0-9a-fA-F]+)"
23 - "E: #CD:12121212"
24 - "E: #CD:4([dD])([0-9a-fA-F]+)"
25 - "E: #CD:34343434"
[all …]
/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
28 #define LSM6DSL_REG_FUNC_CFG_ACCESS 0x01
34 #define LSM6DSL_REG_SENSOR_SYNC_TIME_FRAME 0x04
36 BIT(1) | BIT(0))
37 #define LSM6DSL_SHIFT_SENSOR_SYNC_TIME_FRAME_TPH 0
39 #define LSM6DSL_REG_SENSOR_SYNC_RES_RATIO 0x05
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
41 #define LSM6DSL_SHIFT_SENSOR_SYNC_RES_RATIO 0
43 #define LSM6DSL_REG_FIFO_CTRL1 0x06
[all …]
/Zephyr-latest/drivers/sensor/apds9253/
Dapds9253.h5 * SPDX-License-Identifier: Apache-2.0
13 #define APDS9253_MAIN_CTRL_REG 0x00
14 #define APDS9253_MAIN_CTRL_REG_MASK GENMASK(5, 0)
16 #define APDS9253_MAIN_CTRL_SW_RESET BIT(4)
20 #define APDS9253_LS_MEAS_RATE_REG 0x04
21 #define APDS9253_LS_MEAS_RATE_RES_MASK GENMASK(6, 4)
22 #define APDS9253_LS_MEAS_RATE_RES_20BIT_400MS 0
23 #define APDS9253_LS_MEAS_RATE_RES_19BIT_200MS BIT(4)
25 #define APDS9253_LS_MEAS_RATE_RES_17BIT_50MS (BIT(5) | BIT(4))
27 #define APDS9253_LS_MEAS_RATE_RES_13_3MS (BIT(6) | BIT(4))
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
19 #define LSM9DS0_GYRO_REG_WHO_AM_I_G 0x0F
20 #define LSM9DS0_GYRO_VAL_WHO_AM_I_G 0xD4
22 #define LSM9DS0_GYRO_REG_CTRL_REG1_G 0x20
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
26 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_BW 4
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
34 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_YEN 0
36 #define LSM9DS0_GYRO_REG_CTRL_REG2_G 0x21
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/
DW25Q512JVFIQ_FCB.c2 * Copyright 2021-2024 NXP
5 * SPDX-License-Identifier: Apache-2.0
20 .deviceModeArg = 0x02,
21 .configCmdEnable = 0,
22 .deviceType = 0x1,
25 .sflashA1Size = 0x4000000U,
26 .sflashA2Size = 0,
27 .sflashB1Size = 0,
28 .sflashB2Size = 0,
31 [0] = FC_FLEXSPI_LUT_SEQ(
[all …]

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