Lines Matching +full:0 +full:- +full:4

5  * SPDX-License-Identifier: Apache-2.0
13 #define APDS9253_MAIN_CTRL_REG      0x00
14 #define APDS9253_MAIN_CTRL_REG_MASK GENMASK(5, 0)
16 #define APDS9253_MAIN_CTRL_SW_RESET BIT(4)
20 #define APDS9253_LS_MEAS_RATE_REG             0x04
21 #define APDS9253_LS_MEAS_RATE_RES_MASK        GENMASK(6, 4)
22 #define APDS9253_LS_MEAS_RATE_RES_20BIT_400MS 0
23 #define APDS9253_LS_MEAS_RATE_RES_19BIT_200MS BIT(4)
25 #define APDS9253_LS_MEAS_RATE_RES_17BIT_50MS  (BIT(5) | BIT(4))
27 #define APDS9253_LS_MEAS_RATE_RES_13_3MS      (BIT(6) | BIT(4))
28 #define APDS9253_LS_MEAS_RATE_MES_MASK        GENMASK(2, 0)
29 #define APDS9253_LS_MEAS_RATE_MES_2000MS      (BIT(2) | BIT(1) | BIT(0))
30 #define APDS9253_LS_MEAS_RATE_MES_1000MS      (BIT(2) | BIT(0))
32 #define APDS9253_LS_MEAS_RATE_MES_200MS       (BIT(1) | BIT(0))
34 #define APDS9253_LS_MEAS_RATE_MES_50MS        BIT(0)
35 #define APDS9253_LS_MEAS_RATE_MES_25MS        0
37 #define APDS9253_LS_GAIN_REG      0x05
38 #define APDS9253_LS_GAIN_MASK     GENMASK(2, 0)
40 #define APDS9253_LS_GAIN_RANGE_9  (BIT(1) | BIT(0))
42 #define APDS9253_LS_GAIN_RANGE_3  BIT(0) /* default */
43 #define APDS9253_LS_GAIN_RANGE_1  0
45 #define APDS9253_PART_ID          0x06
46 #define APDS9253_DEVICE_PART_ID   0xC0
47 #define APDS9253_PART_ID_REV_MASK GENMASK(3, 0)
48 #define APDS9253_PART_ID_ID_MASK  GENMASK(7, 4)
50 #define APDS9253_MAIN_STATUS_REG          0x07
52 #define APDS9253_MAIN_STATUS_LS_INTERRUPT BIT(4)
56 #define APDS9253_LS_DATA_BASE    0x0A
57 #define APDS9253_LS_DATA_IR_0    0x0A
58 #define APDS9253_LS_DATA_IR_1    0x0B
59 #define APDS9253_LS_DATA_IR_2    0x0C
60 #define APDS9253_LS_DATA_GREEN_0 0x0D
61 #define APDS9253_LS_DATA_GREEN_1 0x0E
62 #define APDS9253_LS_DATA_GREEN_2 0x0F
63 #define APDS9253_LS_DATA_BLUE_0  0x10
64 #define APDS9253_LS_DATA_BLUE_1  0x11
65 #define APDS9253_LS_DATA_BLUE_2  0x12
66 #define APDS9253_LS_DATA_RED_0   0x13
67 #define APDS9253_LS_DATA_RED_1   0x14
68 #define APDS9253_LS_DATA_RED_2   0x15
70 #define APDS9253_INT_CFG                 0x19
71 #define APDS9253_INT_CFG_LS_INT_SEL_IR   0
72 #define APDS9253_INT_CFG_LS_INT_SEL_ALS  BIT(4) /* default */
74 #define APDS9253_INT_CFG_LS_INT_SEL_BLUE (BIT(5) | BIT(4))
78 #define APDS9253_INT_PST        0x1A
79 #define APDS9253_LS_THRES_UP_0  0x21
80 #define APDS9253_LS_THRES_UP_1  0x22
81 #define APDS9253_LS_THRES_UP_2  0x23
82 #define APDS9253_LS_THRES_LOW_0 0x24
83 #define APDS9253_LS_THRES_LOW_1 0x25
84 #define APDS9253_LS_THRES_LOW_2 0x26
85 #define APDS9253_LS_THRES_VAR   0x27
86 #define APDS9253_DK_CNT_STOR    0x29
101 	uint32_t sample_crgb[4];