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/Zephyr-Core-3.5.0/boards/arm/v2m_musca_b1/
Dv2m_musca_b1-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 reg = <0x3000 0x1000>;
10 interrupts = <6 3>;
15 reg = <0x4000 0x1000>;
16 interrupts = <7 3>;
20 compatible = "arm,cmsdk-timer";
21 reg = <0x10c000 0x1000>;
22 interrupts = <3 3>;
27 reg = <0x105000 0x1000>;
28 interrupts = <39 3 40 3 41 3 43 3>;
[all …]
/Zephyr-Core-3.5.0/boards/arm/v2m_musca_s1/
Dv2m_musca_s1-common.dtsi2 * Copyright (c) 2019-2020 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
9 reg = <0x3000 0x1000>;
10 interrupts = <6 3>;
15 reg = <0x4000 0x1000>;
16 interrupts = <7 3>;
20 compatible = "arm,cmsdk-timer";
21 reg = <0x10b000 0x1000>;
22 interrupts = <33 3>;
27 reg = <0x101000 0x1000>;
[all …]
/Zephyr-Core-3.5.0/modules/hal_nordic/nrfx/
Dnrfx_config_nrf51.h2 * Copyright (c) 2017 - 2023, Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
18 * Integer value. Minimum: 0 Maximum: 3
21 #define NRFX_DEFAULT_IRQ_PRIORITY 3
27 * Boolean. Accepted values 0 and 1.
30 #define NRFX_ADC_ENABLED 0
36 * Integer value. Minimum: 0 Maximum: 3
45 * Boolean. Accepted values 0 and 1.
48 #define NRFX_ADC_CONFIG_LOG_ENABLED 0
56 * - Off = 0
[all …]
/Zephyr-Core-3.5.0/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
24 #define BT_UUID_SERVICE_A BT_UUID_DECLARE_16(0xa00a)
29 #define BT_UUID_VALUE_V1 BT_UUID_DECLARE_16(0xb001)
34 #define BT_UUID_VALUE_V2 BT_UUID_DECLARE_16(0xb002)
39 #define BT_UUID_VALUE_V3 BT_UUID_DECLARE_16(0xb003)
41 static uint8_t value_v1_value = 0x01;
43 '1', '1', '1', '1', '1', '2', '2', '2', '2', '2', '3', '3', '3',
44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/clock/
Dstm32g4_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 #define STM32_CLOCK_BUS_AHB1 0x048
11 #define STM32_CLOCK_BUS_AHB2 0x04c
12 #define STM32_CLOCK_BUS_AHB3 0x050
13 #define STM32_CLOCK_BUS_APB1 0x058
14 #define STM32_CLOCK_BUS_APB1_2 0x05c
15 #define STM32_CLOCK_BUS_APB2 0x060
24 #define STM32_SRC_HSI 0x001
25 #define STM32_SRC_HSI48 0x002
26 #define STM32_SRC_HSE 0x003
[all …]
Dstm32u5_clock.h4 * SPDX-License-Identifier: Apache-2.0
14 #define STM32_SRC_PLL1_P 0x001
15 #define STM32_SRC_PLL1_Q 0x002
16 #define STM32_SRC_PLL1_R 0x003
17 #define STM32_SRC_PLL2_P 0x004
18 #define STM32_SRC_PLL2_Q 0x005
19 #define STM32_SRC_PLL2_R 0x006
20 #define STM32_SRC_PLL3_P 0x007
21 #define STM32_SRC_PLL3_Q 0x008
22 #define STM32_SRC_PLL3_R 0x009
[all …]
Dstm32l4_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 #define STM32_CLOCK_BUS_AHB1 0x048
11 #define STM32_CLOCK_BUS_AHB2 0x04c
12 #define STM32_CLOCK_BUS_AHB3 0x050
13 #define STM32_CLOCK_BUS_APB1 0x058
14 #define STM32_CLOCK_BUS_APB1_2 0x05c
15 #define STM32_CLOCK_BUS_APB2 0x060
24 #define STM32_SRC_HSI 0x001
25 #define STM32_SRC_HSI48 0x002
26 #define STM32_SRC_LSE 0x003
[all …]
Dstm32g0_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 #define STM32_CLOCK_BUS_IOP 0x034
11 #define STM32_CLOCK_BUS_AHB1 0x038
12 #define STM32_CLOCK_BUS_APB1 0x03c
13 #define STM32_CLOCK_BUS_APB1_2 0x040
22 #define STM32_SRC_HSI 0x001
23 #define STM32_SRC_HSI48 0x002
24 #define STM32_SRC_MSI 0x003
25 #define STM32_SRC_HSE 0x004
26 #define STM32_SRC_LSE 0x005
[all …]
Dstm32wl_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 #define STM32_CLOCK_BUS_AHB1 0x048
11 #define STM32_CLOCK_BUS_AHB2 0x04c
12 #define STM32_CLOCK_BUS_AHB3 0x050
13 #define STM32_CLOCK_BUS_APB1 0x058
14 #define STM32_CLOCK_BUS_APB1_2 0x05c
15 #define STM32_CLOCK_BUS_APB2 0x060
16 #define STM32_CLOCK_BUS_APB3 0x064
25 #define STM32_SRC_HSI 0x001
26 #define STM32_SRC_LSE 0x002
[all …]
/Zephyr-Core-3.5.0/boards/arm/mps2_an521/
Dmps2_an521-common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 sysclk: system-clock {
8 compatible = "fixed-clock";
9 clock-frequency = <25000000>;
10 #clock-cells = <0>;
13 timer0: timer@0 {
14 compatible = "arm,cmsdk-timer";
15 reg = <0x0 0x1000>;
16 interrupts = <3 3>;
20 compatible = "arm,cmsdk-timer";
[all …]
/Zephyr-Core-3.5.0/dts/arm/infineon/
Dxmc4500_F100x1024-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
Dxmc4700_F144x2048-intc.dtsi3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
10 XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
11 XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
12 XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
13 XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
16 XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
[all …]
Dxmc4700_F144x2048-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
10 /omit-if-no-ref/ uart_tx_p0_1_u1c1: uart_tx_p0_1_u1c1 {
11 pinmux = <XMC4XXX_PINMUX_SET(0, 1, 2)>;
13 /omit-if-no-ref/ uart_tx_p0_5_u1c0: uart_tx_p0_5_u1c0 {
14 pinmux = <XMC4XXX_PINMUX_SET(0, 5, 2)>;
16 /omit-if-no-ref/ uart_tx_p1_5_u0c0: uart_tx_p1_5_u0c0 {
19 /omit-if-no-ref/ uart_tx_p1_7_u0c0: uart_tx_p1_7_u0c0 {
22 /omit-if-no-ref/ uart_tx_p1_9_u1c1: uart_tx_p1_9_u1c1 {
25 /omit-if-no-ref/ uart_tx_p1_15_u1c0: uart_tx_p1_15_u1c0 {
[all …]
Dxmc4500_F100x1024-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
10 /omit-if-no-ref/ uart_tx_p0_1_u1c1: uart_tx_p0_1_u1c1 {
11 pinmux = <XMC4XXX_PINMUX_SET(0, 1, 2)>;
13 /omit-if-no-ref/ uart_tx_p0_5_u1c0: uart_tx_p0_5_u1c0 {
14 pinmux = <XMC4XXX_PINMUX_SET(0, 5, 2)>;
16 /omit-if-no-ref/ uart_tx_p1_5_u0c0: uart_tx_p1_5_u0c0 {
19 /omit-if-no-ref/ uart_tx_p1_7_u0c0: uart_tx_p1_7_u0c0 {
22 /omit-if-no-ref/ uart_tx_p2_5_u0c1: uart_tx_p2_5_u0c1 {
25 /omit-if-no-ref/ uart_tx_p2_14_u1c0: uart_tx_p2_14_u1c0 {
[all …]
/Zephyr-Core-3.5.0/subsys/net/ip/
Dnet_tc_mapping.h10 * SPDX-License-Identifier: Apache-2.0
19 * according to 802.1Q - table I-2.
23 * 0 (default) BE Best effort
25 * 3 CA Critical applications
36 #if defined(CONFIG_NET_TC_MAPPING_STRICT) && (NET_TC_COUNT > 0)
39 * implementations that do not support the credit-based shaper transmission
41 * Ref: 802.1Q - chapter 8.6.6 - table 8-4
45 static const uint8_t priority2tc_strict_1[] = {0, 0, 0, 0, 0, 0, 0, 0};
48 static const uint8_t priority2tc_strict_2[] = {0, 0, 0, 0, 1, 1, 1, 1};
50 #if NET_TC_TX_COUNT == 3 || NET_TC_RX_COUNT == 3
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77961.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
14 #define PIN_SD0_CLK RCAR_GP_PIN(3, 0)
15 #define PIN_SD0_CMD RCAR_GP_PIN(3, 1)
16 #define PIN_SD0_DATA0 RCAR_GP_PIN(3, 2)
17 #define PIN_SD0_DATA1 RCAR_GP_PIN(3, 3)
18 #define PIN_SD0_DATA2 RCAR_GP_PIN(3, 4)
19 #define PIN_SD0_DATA3 RCAR_GP_PIN(3, 5)
20 #define PIN_SD0_CD RCAR_GP_PIN(3, 12)
[all …]
/Zephyr-Core-3.5.0/tests/bluetooth/tester/src/btp/
Dbtp_bap.h1 /* btp_bap.h - Bluetooth tester headers */
6 * SPDX-License-Identifier: Apache-2.0
10 #define BTP_BAP_READ_SUPPORTED_COMMANDS 0x01
12 uint8_t data[0];
15 #define BTP_BAP_DISCOVER 0x02
20 #define BTP_BAP_DISCOVERY_STATUS_SUCCESS 0x00
21 #define BTP_BAP_DISCOVERY_STATUS_FAILED 0x01
23 #define BTP_BAP_SEND 0x03
28 uint8_t data[0];
35 #define BTP_BAP_BROADCAST_SOURCE_SETUP 0x04
[all …]
/Zephyr-Core-3.5.0/dts/arm/nuvoton/npcx/
Dnpcx-miwus-wui-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
12 /* MIWU table 0 */
14 wui_io80: wui0-1-0 {
15 miwus = <&miwu0 0 0>; /* GPIO80 */
17 wui_io81: wui0-1-1 {
18 miwus = <&miwu0 0 1>; /* GPIO81 */
20 wui_io82: wui0-1-2 {
21 miwus = <&miwu0 0 2>; /* GPIO82 */
[all …]
/Zephyr-Core-3.5.0/soc/arm64/renesas_rcar/gen3/
Dpfc_r8a77961.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
13 { 0x0334, {
14 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
15 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
16 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
17 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
18 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
19 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
22 { 0x0338, {
[all …]
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/reg/
Dmec_peci.h4 * SPDX-License-Identifier: Apache-2.0
14 #define MCHP_PECI_WR_DATA_REG_OFS 0u
15 #define MCHP_PECI_WR_DATA_MASK 0xffu
19 #define MCHP_PECI_RD_DATA_MASK 0xffu
23 #define MCHP_PECI_CTRL_MASK 0xe9u
24 #define MCHP_PECI_CTRL_PD_POS 0
26 #define MCHP_PECI_CTRL_RST_POS 3
35 /* Status 1 register. RW1C and read-only bits. */
36 #define MCHP_PECI_STS1_REG_OFS 0x0cu
37 #define MCHP_PECI_STS1_MASK 0xbfu
[all …]
/Zephyr-Core-3.5.0/dts/xtensa/espressif/esp32/
Desp32_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/gpio/gpio.h>
10 #include <zephyr/dt-bindings/i2c/i2c.h>
11 #include <zephyr/dt-bindings/clock/esp32_clock.h>
12 #include <zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h>
13 #include <dt-bindings/pinctrl/esp32-pinctrl.h>
14 #include <zephyr/dt-bindings/pwm/pwm.h>
20 zephyr,flash-controller = &flash;
24 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/boards/arm/mps3_an547/
Dmps3_an547-common.dtsi2 * Copyright (c) 2019-2021 Linaro Limited
4 * SPDX-License-Identifier: Apache-2.0
7 sysclk: system-clock {
8 compatible = "fixed-clock";
9 clock-frequency = <25000000>;
10 #clock-cells = <0>;
14 compatible = "arm,cmsdk-gpio";
15 reg = <0x1100000 0x1000>;
16 interrupts = <69 3>;
17 gpio-controller;
[all …]
/Zephyr-Core-3.5.0/samples/subsys/zbus/msg_subscriber/src/
Dmain.c3 * SPDX-License-Identifier: Apache-2.0
24 total_allocated -= bytes; in on_heap_free()
51 ZBUS_MSG_INIT(.x = 0, .y = 0, .z = 0) /* Initial value */
58 LOG_INF("From listener foo_lis -> Acc x=%d, y=%d, z=%d", acc->x, acc->y, acc->z); in listener_callback_example()
97 LOG_INF("From msg subscriber %s -> Acc x=%d, y=%d, z=%d", zbus_obs_name(subscriber), in msg_subscriber_task()
103 NULL, NULL, 3, 0, 0);
105 NULL, NULL, 3, 0, 0);
107 NULL, NULL, 3, 0, 0);
109 NULL, NULL, 3, 0, 0);
111 NULL, NULL, 3, 0, 0);
[all …]
/Zephyr-Core-3.5.0/dts/arm/cypress/
Dpsoc6_cm0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
12 cpu@0 {
13 compatible = "arm,cortex-m0+";
16 /delete-node/ cpu@1;
21 /* see cypress,psoc6-int-mux.yaml */
22 compatible = "cypress,psoc6-intmux";
23 reg = <0x40210020 0x20>;
24 ranges = <0x0 0x40210020 0x20>;
26 #address-cells = <1>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec172xnsz.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/mchp_xec_pcr.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
13 #include <zephyr/dt-bindings/i2c/i2c.h>
14 #include <zephyr/dt-bindings/interrupt-controller/mchp-xec-ecia.h>
18 #include "mec172x/mec172x-vw-routing.dtsi"
22 #address-cells = <1>;
[all …]

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