1 /*
2 * Copyright (c) 2023 EPAM Systems
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7
8 #include "pinctrl_soc.h"
9 #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a77961.h>
10
11 const struct pfc_drive_reg pfc_drive_regs[] = {
12 /* DRVCTRL13 */
13 { 0x0334, {
14 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
15 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
16 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
17 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
18 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
19 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
20 } },
21 /* DRVCTRL14 */
22 { 0x0338, {
23 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
24 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
25 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
26 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
27 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
28 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
29 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
30 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
31 } },
32 /* DRVCTRL15 */
33 { 0x033c, {
34 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
35 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
36 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
37 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
38 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
39 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
40 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
41 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
42 } },
43 /* DRVCTRL16 */
44 { 0x0340, {
45 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
46 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
47 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
48 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
49 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
50 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
51 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
52 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
53 } },
54 /* DRVCTRL17 */
55 { 0x0344, {
56 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
57 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
58 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
59 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
60 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
61 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
62 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
63 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
64 } },
65 /* DRVCTRL18 */
66 { 0x0348, {
67 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
68 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
69 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
70 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
71 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
72 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
73 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
74 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
75 } },
76 { },
77 };
78
79 #define PFC_BIAS_REG(r1, r2) \
80 .puen = r1, \
81 .pud = r2, \
82 .pins =
83
84 const struct pfc_bias_reg pfc_bias_regs[] = {
85 { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */
86 [0 ... 9] = PIN_NONE,
87 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
88 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
89 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
90 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
91 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
92 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
93 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
94 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
95 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
96 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
97 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
98 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
99 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
100 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
101 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
102 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
103 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
104 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
105 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
106 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
107 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
108 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
109 } },
110 { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */
111 [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
112 [1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
113 [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
114 [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
115 [4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
116 [5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
117 [6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
118 [7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
119 [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
120 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
121 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
122 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
123 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
124 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
125 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
126 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
127 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
128 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
129 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
130 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
131 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
132 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
133 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
134 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
135 [24 ... 31] = PIN_NONE,
136 } },
137 { /* sentinel */ },
138 };
pfc_rcar_get_bias_regs(void)139 const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
140 {
141 return pfc_bias_regs;
142 }
pfc_rcar_get_drive_regs(void)143 const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
144 {
145 return pfc_drive_regs;
146 }
147
