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/hal_gigadevice-latest/pinconfigs/
Dgd32f403xx.yml4 # - GD32F403XX Datasheet (Revision 1.2)
5 # - GD32F403 User Manual (Revision 2.1)
9 # - 144 pins: Z
10 # - 100 pins: V
11 # - 64 pins: R
15 # - 3072Kb Flash, 128Kb SRAM: K
16 # - 2048Kb Flash, 128Kb SRAM: I
17 # - 1024Kb Flash, 128Kb SRAM: G
18 # - 512Kb Flash, 96Kb SRAM: E
19 # - 256Kb Flash, 64Kb SRAM: C
[all …]
Dgd32f350xx.yml4 # - GD32F350XX Datasheet (Revision 1.5)
8 # - 28 pins: G
9 # - 32 pins: K
10 # - 48 pins: C
11 # - 64 pins: R
15 # - 16Kb Flash, 4Kb SRAM: 4
16 # - 32Kb Flash, 6Kb SRAM: 6
17 # - 64Kb Flash, 8Kb SRAM: 8
18 # - 64Kb Flash, 16Kb SRAM: 8(GD32F350R8 only)
19 # - 128Kb Flash, 16Kb SRAM: B
[all …]
Dgd32vf103xx.yml4 # - GD32VF103XX Datasheet (Revision 1.2)
5 # - GD32VF103 User Manual (Revision 1.2)
9 # - 100 pins: V
10 # - 64 pins: R
11 # - 48 pins: C
12 # - 36 pins: T
16 # - 128Kb Flash, 32Kb SRAM: B
17 # - 64Kb Flash, 20Kb SRAM: 8
18 # - 32Kb Flash, 10Kb SRAM: 6
19 # - 16Kb Flash, 6Kb SRAM: 4
[all …]
Dgd32e507xx.yml4 # - GD32E507XX Datasheet (Revision 1.4)
5 # - GD32E50X User Manual (Revision 1.0)
9 # - 144 pins: Z
10 # - 100 pins: V
11 # - 64 pins: R
15 # - 512Kb Flash, 128Kb SRAM: E
16 # - 256Kb Flash, 96Kb SRAM: C
19 # SPDX-License-Identifier: Apache 2.0
26 - pincode: Z
28 - pincode: V
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Dgd32e103xx.yml4 # - GD32E103XX Datasheet (Revision 1.5)
5 # - GD32E103 User Manual (Revision 1.5)
9 # - 100 pins: V
10 # - 64 pins: R
11 # - 48 pins: C
12 # - 36 pins: T
16 # - 128Kb Flash, 32Kb SRAM: B
17 # - 64Kb Flash, 20Kb SRAM: 8
20 # SPDX-License-Identifier: Apache 2.0
27 - pincode: V
[all …]
Dgd32l233xx.yml5 # - GD32L233XX Datasheet (Revision 1.2)
9 # - 32 pins: Q (GD32L233Kx-QFN32)
10 # - 32 pins: K (GD32L233Kx-LQFP32)
11 # - 48 pins: C
12 # - 64 pins: R
16 # - 64Kb Flash, 16Kb SRAM: 8
17 # - 128Kb Flash, 24Kb SRAM: B
18 # - 256Kb Flash, 32Kb SRAM: C
21 # SPDX-License-Identifier: Apache 2.0
28 - pincode: Q
[all …]
Dgd32a503xx.yml4 # - GD32A503XX Datasheet (Revision 1.3)
8 # - 32 pins: K
9 # - 48 pins: C
10 # - 64 pins: R
11 # - 100 pins: V
15 # - 128Kb Flash, 24Kb SRAM: B
16 # - 256Kb Flash, 32Kb SRAM: C
17 # - 384Kb Flash, 48Kb SRAM: D
20 # SPDX-License-Identifier: Apache 2.0
27 - pincode: K
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Dgd32f405xx.yml4 # - GD32F405XX Datasheet (Revision 2.2)
8 # - 64 pins: R
9 # - 100 pins: V
10 # - 144 pins: Z
14 # - 512Kb Flash, 192Kb SRAM: E
15 # - 1024Kb Flash, 192Kb SRAM: G
16 # - 3072Kb Flash, 192Kb SRAM: K
19 # SPDX-License-Identifier: Apache 2.0
26 - pincode: R
28 - pincode: V
[all …]
Dgd32f407xx.yml4 # - GD32F407XX Datasheet (Revision 2.5)
8 # - 64 pins: R
9 # - 100 pins: V
10 # - 144 pins: Z
11 # - 176 pins: I
15 # - 512Kb Flash, 192Kb SRAM: E
16 # - 1024Kb Flash, 192Kb SRAM: G
17 # - 3072Kb Flash, 192Kb SRAM: K
20 # SPDX-License-Identifier: Apache 2.0
27 - pincode: R
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DREADME.md28 - `model` (required): Choose between `afio` or `af`
29 - `series` (required): Series name, e.g. gd32vf103
30 - `variants` (required): Each variant has a different set of valid pin
42 - pincode: V
44 - pincode: R
47 # less peripherals (and so less signals) than B-8.
48 - pincode: R
56 - `signal-configs` (required): A dictionary of signal configurations. Each
61 - `modes` (required): A list containing one or more of these modes: `analog`,
63 - `exclude-memories` (optional): A lit of memories where the signal is not
[all …]
/hal_gigadevice-latest/scripts/
DREADME.md11 pip install -r scripts/requirements.txt
21 pip install -r scripts/requirements-dev.txt
30 pip install -r scripts/requirements-test.txt
Dgd32headers.py6 python3 gd32headers.py [-p /path/to/HAL] [-o /path/to/output_dir]
10 SPDX-License-Identifier: Apache-2.0
40 m = re.match(r"^gd32[a-z0-9]+_([a-z0-9]+)\.h$", header.name)
64 f.write(" * SPDX-License-Identifier: Apache-2.0\n")
77 "-p",
78 "--hal-path",
84 "-o",
85 "--output",
Dgd32pinctrl.py5 python3 gd32pinctrl.py [-i /path/to/configs] [-o /path/to/include]
8 SPDX-License-Identifier: Apache 2.0
40 * SPDX-License-Identifier: Apache 2.0
58 memories = f"({'-'.join((str(m).lower() for m in variant['memories']))})"
59 return f"{series}{pincode}{memories}xx-pinctrl.h"
72 m = re.match(r"P([A-Z])(\d+)", pin_name)
93 f.write(f"\n#include \"{series}xx-afio.h\"\n")
116 f.write("\n#include \"gd32-af.h\"\n")
145 if pincode in signal_cfg.get("exclude-pincodes", []):
149 if set(memories).intersection(signal_cfg.get("exclude-memories", [])):
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/hal_gigadevice-latest/.github/workflows/
Dtest.yml7 runs-on: ubuntu-latest
9 fail-fast: false
11 python-version:
12 - "3.7"
13 - "3.8"
14 - "3.9"
15 - "3.10"
17 - uses: actions/checkout@v1
18 - name: Set up Python
19 uses: actions/setup-python@v1
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/hal_gigadevice-latest/gd32vf103/riscv/drivers/
Driscv_encoding.h59 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
60 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
61 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
180 __asm__ volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \
187 __asm__ volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); })
191 __asm__ volatile ("csrr %0, " #reg : "=r"(__tmp)); \
198 __asm__ volatile ("csrw " #reg ", %0" :: "r"(val)); })
202 __asm__ volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
204 __asm__ volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
209 __asm__ volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
[all …]
Dn200_func.c15 /* Config entry0 cfg to make it NAPOT address mode, and R/W/X okay */ in pmp_open_all_space()
114 delta_mtime = mtime_lo() - start_mtime; in measure_cpu_freq()
118 uint32_t delta_mcycle = read_csr(CSR_MCYCLE) - start_mcycle; in measure_cpu_freq()
120 uint32_t delta_mcycle = read_csr(mcycle) - start_mcycle; in measure_cpu_freq()
240 lvl = lvl >> (8-nlbits); in eclic_set_irq_lvl()
242 lvl = lvl << (8-nlbits); in eclic_set_irq_lvl()
265 intctrl = intctrl >> (8-nlbits); in eclic_get_irq_lvl()
267 uint8_t lvl = intctrl << (8-nlbits); in eclic_get_irq_lvl()
280 uint8_t lvl = lvl_abs << (8-nlbits); in eclic_set_irq_lvl_abs()
302 intctrl = intctrl >> (8-nlbits); in eclic_get_irq_lvl_abs()
[all …]
/hal_gigadevice-latest/gd32vf103/riscv/env_eclipse/
Dinit.c18 //printf("After ECLIC mode enabled, the mtvec value is %x \n\n\r", read_csr(mtvec)); in _init()
21 …// // * In the RISC-V arch, if user mode and PMP supported, then by default if PMP is not conf… in _init()
23 // // * So if switch to user-mode and still want to continue, then you must configure PMP first in _init()
DGD32VF103x4.lds134 *(.gnu.linkonce.r.*)
169 .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
DGD32VF103x6.lds134 *(.gnu.linkonce.r.*)
169 .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
DGD32VF103x8.lds134 *(.gnu.linkonce.r.*)
169 .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
DGD32VF103xB.lds134 *(.gnu.linkonce.r.*)
169 .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
/hal_gigadevice-latest/gd32vf103/riscv/stubs/
Dwrite.c24 if (handle == -1) in __write()
29 for (; bufSize > 0; --bufSize) in __write()
51 _put_char('\r'); in _write()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_can.c5 \version 2020-03-10, V1.0.0, firmware for GD32E50x
6 \version 2021-03-23, V1.2.0, firmware for GD32E50x
161 CAN_ERROR_HANDLE("struct parameter can not be NULL \r\n"); in can_struct_para_init()
167 ((can_parameter_struct*)p_struct)->auto_bus_off_recovery = DISABLE; in can_struct_para_init()
168 ((can_parameter_struct*)p_struct)->auto_retrans = DISABLE; in can_struct_para_init()
169 ((can_parameter_struct*)p_struct)->auto_wake_up = DISABLE; in can_struct_para_init()
170 ((can_parameter_struct*)p_struct)->prescaler = 0x0400U; in can_struct_para_init()
171 ((can_parameter_struct*)p_struct)->rec_fifo_overwrite = DISABLE; in can_struct_para_init()
172 ((can_parameter_struct*)p_struct)->resync_jump_width = CAN_BT_SJW_1TQ; in can_struct_para_init()
173 ((can_parameter_struct*)p_struct)->time_segment_1 = CAN_BT_BS1_3TQ; in can_struct_para_init()
[all …]
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_spi.c5 \version 2021-08-04, V1.0.0, firmware for GD32L23x
94 spi_struct->device_mode = SPI_SLAVE; in spi_struct_para_init()
95 spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; in spi_struct_para_init()
96 spi_struct->frame_size = SPI_FRAMESIZE_8BIT; in spi_struct_para_init()
97 spi_struct->nss = SPI_NSS_HARD; in spi_struct_para_init()
98 spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; in spi_struct_para_init()
99 spi_struct->prescale = SPI_PSC_2; in spi_struct_para_init()
100 spi_struct->endian = SPI_ENDIAN_MSB; in spi_struct_para_init()
141 reg1 |= spi_struct->device_mode; in spi_init()
143 reg1 |= spi_struct->trans_mode; in spi_init()
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/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_can.c5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx
6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx
7 \version 2019-11-27, V2.0.1, firmware for GD32F4xx
8 \version 2020-07-14, V2.0.2, firmware for GD32F4xx
9 \version 2020-09-30, V2.1.0, firmware for GD32F4xx
10 \version 2021-12-28, V2.1.1, firmware for GD32F4xx
11 \version 2022-03-09, V3.0.0, firmware for GD32F4xx
82 ((can_parameter_struct *)p_struct)->auto_bus_off_recovery = DISABLE; in can_struct_para_init()
83 ((can_parameter_struct *)p_struct)->auto_retrans = ENABLE; in can_struct_para_init()
84 ((can_parameter_struct *)p_struct)->auto_wake_up = DISABLE; in can_struct_para_init()
[all …]

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