Lines Matching +full:- +full:r

5     \version 2021-08-04, V1.0.0, firmware for GD32L23x
94 spi_struct->device_mode = SPI_SLAVE; in spi_struct_para_init()
95 spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; in spi_struct_para_init()
96 spi_struct->frame_size = SPI_FRAMESIZE_8BIT; in spi_struct_para_init()
97 spi_struct->nss = SPI_NSS_HARD; in spi_struct_para_init()
98 spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; in spi_struct_para_init()
99 spi_struct->prescale = SPI_PSC_2; in spi_struct_para_init()
100 spi_struct->endian = SPI_ENDIAN_MSB; in spi_struct_para_init()
141 reg1 |= spi_struct->device_mode; in spi_init()
143 reg1 |= spi_struct->trans_mode; in spi_init()
145 reg1 |= spi_struct->nss; in spi_init()
147 reg1 |= spi_struct->endian; in spi_init()
149 reg1 |= spi_struct->clock_polarity_phase; in spi_init()
151 reg1 |= spi_struct->prescale; in spi_init()
154 …if((SPI_FRAMESIZE_8BIT != spi_struct->frame_size) && (SPI_FRAMESIZE_16BIT != spi_struct->frame_siz… in spi_init()
157 reg1 |= (spi_struct->frame_size & SPI_FRAMESIZE_MASK); in spi_init()
165 reg2 |= spi_struct->device_mode; in spi_init()
167 reg2 |= spi_struct->trans_mode; in spi_init()
169 reg2 |= spi_struct->nss; in spi_init()
171 reg2 |= spi_struct->endian; in spi_init()
173 reg2 |= spi_struct->clock_polarity_phase; in spi_init()
175 reg2 |= spi_struct->prescale; in spi_init()
180 reg3 |= spi_struct->frame_size; in spi_init()
290 SPI_ERROR_HANDLE("the parameter can not be 0 \r\n"); in i2s_psc_config()
301 SPI_ERROR_HANDLE("the peripheral must be SPI1 \r\n"); in i2s_psc_config()
341 i2sdiv = ((clks - i2sof) / 2U); in i2s_psc_config()
499 \param[in] data: 16-bit data
512 \retval 16-bit data
524 \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode
525 \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode
556 \retval 16-bit CRC polynomial
604 \retval 16-bit CRC value
731 \arg SPI_HALFWORD_ACCESS: half-word access to FIFO
931 \arg SPI_FLAG_TRANS: transmit on-going flag
938 \arg I2S_FLAG_TRANS: transmit on-going flag