1 /* See LICENSE for license details.*/ 2 3 #ifndef RISCV_CSR_ENCODING_H 4 #define RISCV_CSR_ENCODING_H 5 6 #define MSTATUS_UIE 0x00000001 7 #define MSTATUS_SIE 0x00000002 8 #define MSTATUS_HIE 0x00000004 9 #define MSTATUS_MIE 0x00000008 10 #define MSTATUS_UPIE 0x00000010 11 #define MSTATUS_SPIE 0x00000020 12 #define MSTATUS_HPIE 0x00000040 13 #define MSTATUS_MPIE 0x00000080 14 #define MSTATUS_SPP 0x00000100 15 #define MSTATUS_MPP 0x00001800 16 #define MSTATUS_FS 0x00006000 17 #define MSTATUS_XS 0x00018000 18 #define MSTATUS_MPRV 0x00020000 19 #define MSTATUS_PUM 0x00040000 20 #define MSTATUS_MXR 0x00080000 21 #define MSTATUS_VM 0x1F000000 22 #define MSTATUS32_SD 0x80000000 23 #define MSTATUS64_SD 0x8000000000000000 24 25 26 #define SSTATUS_UIE 0x00000001 27 #define SSTATUS_SIE 0x00000002 28 #define SSTATUS_UPIE 0x00000010 29 #define SSTATUS_SPIE 0x00000020 30 #define SSTATUS_SPP 0x00000100 31 #define SSTATUS_FS 0x00006000 32 #define SSTATUS_XS 0x00018000 33 #define SSTATUS_PUM 0x00040000 34 #define SSTATUS32_SD 0x80000000 35 #define SSTATUS64_SD 0x8000000000000000 36 37 #define DCSR_XDEBUGVER (3U<<30) 38 #define DCSR_NDRESET (1<<29) 39 #define DCSR_FULLRESET (1<<28) 40 #define DCSR_EBREAKM (1<<15) 41 #define DCSR_EBREAKH (1<<14) 42 #define DCSR_EBREAKS (1<<13) 43 #define DCSR_EBREAKU (1<<12) 44 #define DCSR_STOPCYCLE (1<<10) 45 #define DCSR_STOPTIME (1<<9) 46 #define DCSR_CAUSE (7<<6) 47 #define DCSR_DEBUGINT (1<<5) 48 #define DCSR_HALT (1<<3) 49 #define DCSR_STEP (1<<2) 50 #define DCSR_PRV (3<<0) 51 52 #define DCSR_CAUSE_NONE 0 53 #define DCSR_CAUSE_SWBP 1 54 #define DCSR_CAUSE_HWBP 2 55 #define DCSR_CAUSE_DEBUGINT 3 56 #define DCSR_CAUSE_STEP 4 57 #define DCSR_CAUSE_HALT 5 58 59 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 60 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 61 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 62 63 #define MCONTROL_SELECT (1<<19) 64 #define MCONTROL_TIMING (1<<18) 65 #define MCONTROL_ACTION (0x3f<<12) 66 #define MCONTROL_CHAIN (1<<11) 67 #define MCONTROL_MATCH (0xf<<7) 68 #define MCONTROL_M (1<<6) 69 #define MCONTROL_H (1<<5) 70 #define MCONTROL_S (1<<4) 71 #define MCONTROL_U (1<<3) 72 #define MCONTROL_EXECUTE (1<<2) 73 #define MCONTROL_STORE (1<<1) 74 #define MCONTROL_LOAD (1<<0) 75 76 #define MCONTROL_TYPE_NONE 0 77 #define MCONTROL_TYPE_MATCH 2 78 79 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 80 #define MCONTROL_ACTION_DEBUG_MODE 1 81 #define MCONTROL_ACTION_TRACE_START 2 82 #define MCONTROL_ACTION_TRACE_STOP 3 83 #define MCONTROL_ACTION_TRACE_EMIT 4 84 85 #define MCONTROL_MATCH_EQUAL 0 86 #define MCONTROL_MATCH_NAPOT 1 87 #define MCONTROL_MATCH_GE 2 88 #define MCONTROL_MATCH_LT 3 89 #define MCONTROL_MATCH_MASK_LOW 4 90 #define MCONTROL_MATCH_MASK_HIGH 5 91 92 #define MIP_SSIP (1 << IRQ_S_SOFT) 93 #define MIP_HSIP (1 << IRQ_H_SOFT) 94 #define MIP_MSIP (1 << IRQ_M_SOFT) 95 #define MIP_STIP (1 << IRQ_S_TIMER) 96 #define MIP_HTIP (1 << IRQ_H_TIMER) 97 #define MIP_MTIP (1 << IRQ_M_TIMER) 98 #define MIP_SEIP (1 << IRQ_S_EXT) 99 #define MIP_HEIP (1 << IRQ_H_EXT) 100 #define MIP_MEIP (1 << IRQ_M_EXT) 101 102 #define MIE_SSIE MIP_SSIP 103 #define MIE_HSIE MIP_HSIP 104 #define MIE_MSIE MIP_MSIP 105 #define MIE_STIE MIP_STIP 106 #define MIE_HTIE MIP_HTIP 107 #define MIE_MTIE MIP_MTIP 108 #define MIE_SEIE MIP_SEIP 109 #define MIE_HEIE MIP_HEIP 110 #define MIE_MEIE MIP_MEIP 111 112 #define SIP_SSIP MIP_SSIP 113 #define SIP_STIP MIP_STIP 114 115 #define PRV_U 0 116 #define PRV_S 1 117 #define PRV_H 2 118 #define PRV_M 3 119 120 #define VM_MBARE 0 121 #define VM_MBB 1 122 #define VM_MBBID 2 123 #define VM_SV32 8 124 #define VM_SV39 9 125 #define VM_SV48 10 126 127 #define IRQ_S_SOFT 1 128 #define IRQ_H_SOFT 2 129 #define IRQ_M_SOFT 3 130 #define IRQ_S_TIMER 5 131 #define IRQ_H_TIMER 6 132 #define IRQ_M_TIMER 7 133 #define IRQ_S_EXT 9 134 #define IRQ_H_EXT 10 135 #define IRQ_M_EXT 11 136 #define IRQ_COP 12 137 #define IRQ_HOST 13 138 139 #define DEFAULT_RSTVEC 0x00001000 140 #define DEFAULT_NMIVEC 0x00001004 141 #define DEFAULT_MTVEC 0x00001010 142 #define CONFIG_STRING_ADDR 0x0000100C 143 #define EXT_IO_BASE 0x40000000 144 #define DRAM_BASE 0x80000000 145 146 /* page table entry (PTE) fields */ 147 #define PTE_V 0x001 /* Valid */ 148 #define PTE_R 0x002 /* Read */ 149 #define PTE_W 0x004 /* Write */ 150 #define PTE_X 0x008 /* Execute */ 151 #define PTE_U 0x010 /* User */ 152 #define PTE_G 0x020 /* Global */ 153 #define PTE_A 0x040 /* Accessed */ 154 #define PTE_D 0x080 /* Dirty */ 155 #define PTE_SOFT 0x300 /* Reserved for Software */ 156 157 #define PTE_PPN_SHIFT 10 158 159 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 160 161 #ifdef __riscv 162 163 #ifdef __riscv64 164 # define MSTATUS_SD MSTATUS64_SD 165 # define SSTATUS_SD SSTATUS64_SD 166 # define RISCV_PGLEVEL_BITS 9 167 #else 168 # define MSTATUS_SD MSTATUS32_SD 169 # define SSTATUS_SD SSTATUS32_SD 170 # define RISCV_PGLEVEL_BITS 10 171 #endif 172 #define RISCV_PGSHIFT 12 173 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 174 175 #ifndef __ASSEMBLER__ 176 177 #ifdef __GNUC__ 178 179 #define read_fpu(reg) ({ unsigned long __tmp; \ 180 __asm__ volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ 181 __tmp; }) 182 183 #define write_fpu(reg, val) ({ \ 184 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 185 __asm__ volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ 186 else \ 187 __asm__ volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) 188 189 190 #define read_csr(reg) ({ unsigned long __tmp; \ 191 __asm__ volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 192 __tmp; }) 193 194 #define write_csr(reg, val) ({ \ 195 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 196 __asm__ volatile ("csrw " #reg ", %0" :: "i"(val)); \ 197 else \ 198 __asm__ volatile ("csrw " #reg ", %0" :: "r"(val)); }) 199 200 #define swap_csr(reg, val) ({ unsigned long __tmp; \ 201 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ 202 __asm__ volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ 203 else \ 204 __asm__ volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ 205 __tmp; }) 206 207 #define set_csr(reg, bit) ({ unsigned long __tmp; \ 208 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 209 __asm__ volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 210 else \ 211 __asm__ volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 212 __tmp; }) 213 214 #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 215 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ 216 __asm__ volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ 217 else \ 218 __asm__ volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ 219 __tmp; }) 220 221 #define rdtime() read_csr(time) 222 #define rdcycle() read_csr(cycle) 223 #define rdinstret() read_csr(instret) 224 #endif 225 226 #endif 227 228 #endif 229 230 #endif 231 /* Automatically generated by parse-opcodes */ 232 #ifndef RISCV_ENCODING_H 233 #define RISCV_ENCODING_H 234 #define MATCH_BEQ 0x63 235 #define MASK_BEQ 0x707f 236 #define MATCH_BNE 0x1063 237 #define MASK_BNE 0x707f 238 #define MATCH_BLT 0x4063 239 #define MASK_BLT 0x707f 240 #define MATCH_BGE 0x5063 241 #define MASK_BGE 0x707f 242 #define MATCH_BLTU 0x6063 243 #define MASK_BLTU 0x707f 244 #define MATCH_BGEU 0x7063 245 #define MASK_BGEU 0x707f 246 #define MATCH_JALR 0x67 247 #define MASK_JALR 0x707f 248 #define MATCH_JAL 0x6f 249 #define MASK_JAL 0x7f 250 #define MATCH_LUI 0x37 251 #define MASK_LUI 0x7f 252 #define MATCH_AUIPC 0x17 253 #define MASK_AUIPC 0x7f 254 #define MATCH_ADDI 0x13 255 #define MASK_ADDI 0x707f 256 #define MATCH_SLLI 0x1013 257 #define MASK_SLLI 0xfc00707f 258 #define MATCH_SLTI 0x2013 259 #define MASK_SLTI 0x707f 260 #define MATCH_SLTIU 0x3013 261 #define MASK_SLTIU 0x707f 262 #define MATCH_XORI 0x4013 263 #define MASK_XORI 0x707f 264 #define MATCH_SRLI 0x5013 265 #define MASK_SRLI 0xfc00707f 266 #define MATCH_SRAI 0x40005013 267 #define MASK_SRAI 0xfc00707f 268 #define MATCH_ORI 0x6013 269 #define MASK_ORI 0x707f 270 #define MATCH_ANDI 0x7013 271 #define MASK_ANDI 0x707f 272 #define MATCH_ADD 0x33 273 #define MASK_ADD 0xfe00707f 274 #define MATCH_SUB 0x40000033 275 #define MASK_SUB 0xfe00707f 276 #define MATCH_SLL 0x1033 277 #define MASK_SLL 0xfe00707f 278 #define MATCH_SLT 0x2033 279 #define MASK_SLT 0xfe00707f 280 #define MATCH_SLTU 0x3033 281 #define MASK_SLTU 0xfe00707f 282 #define MATCH_XOR 0x4033 283 #define MASK_XOR 0xfe00707f 284 #define MATCH_SRL 0x5033 285 #define MASK_SRL 0xfe00707f 286 #define MATCH_SRA 0x40005033 287 #define MASK_SRA 0xfe00707f 288 #define MATCH_OR 0x6033 289 #define MASK_OR 0xfe00707f 290 #define MATCH_AND 0x7033 291 #define MASK_AND 0xfe00707f 292 #define MATCH_ADDIW 0x1b 293 #define MASK_ADDIW 0x707f 294 #define MATCH_SLLIW 0x101b 295 #define MASK_SLLIW 0xfe00707f 296 #define MATCH_SRLIW 0x501b 297 #define MASK_SRLIW 0xfe00707f 298 #define MATCH_SRAIW 0x4000501b 299 #define MASK_SRAIW 0xfe00707f 300 #define MATCH_ADDW 0x3b 301 #define MASK_ADDW 0xfe00707f 302 #define MATCH_SUBW 0x4000003b 303 #define MASK_SUBW 0xfe00707f 304 #define MATCH_SLLW 0x103b 305 #define MASK_SLLW 0xfe00707f 306 #define MATCH_SRLW 0x503b 307 #define MASK_SRLW 0xfe00707f 308 #define MATCH_SRAW 0x4000503b 309 #define MASK_SRAW 0xfe00707f 310 #define MATCH_LB 0x3 311 #define MASK_LB 0x707f 312 #define MATCH_LH 0x1003 313 #define MASK_LH 0x707f 314 #define MATCH_LW 0x2003 315 #define MASK_LW 0x707f 316 #define MATCH_LD 0x3003 317 #define MASK_LD 0x707f 318 #define MATCH_LBU 0x4003 319 #define MASK_LBU 0x707f 320 #define MATCH_LHU 0x5003 321 #define MASK_LHU 0x707f 322 #define MATCH_LWU 0x6003 323 #define MASK_LWU 0x707f 324 #define MATCH_SB 0x23 325 #define MASK_SB 0x707f 326 #define MATCH_SH 0x1023 327 #define MASK_SH 0x707f 328 #define MATCH_SW 0x2023 329 #define MASK_SW 0x707f 330 #define MATCH_SD 0x3023 331 #define MASK_SD 0x707f 332 #define MATCH_FENCE 0xf 333 #define MASK_FENCE 0x707f 334 #define MATCH_FENCE_I 0x100f 335 #define MASK_FENCE_I 0x707f 336 #define MATCH_MUL 0x2000033 337 #define MASK_MUL 0xfe00707f 338 #define MATCH_MULH 0x2001033 339 #define MASK_MULH 0xfe00707f 340 #define MATCH_MULHSU 0x2002033 341 #define MASK_MULHSU 0xfe00707f 342 #define MATCH_MULHU 0x2003033 343 #define MASK_MULHU 0xfe00707f 344 #define MATCH_DIV 0x2004033 345 #define MASK_DIV 0xfe00707f 346 #define MATCH_DIVU 0x2005033 347 #define MASK_DIVU 0xfe00707f 348 #define MATCH_REM 0x2006033 349 #define MASK_REM 0xfe00707f 350 #define MATCH_REMU 0x2007033 351 #define MASK_REMU 0xfe00707f 352 #define MATCH_MULW 0x200003b 353 #define MASK_MULW 0xfe00707f 354 #define MATCH_DIVW 0x200403b 355 #define MASK_DIVW 0xfe00707f 356 #define MATCH_DIVUW 0x200503b 357 #define MASK_DIVUW 0xfe00707f 358 #define MATCH_REMW 0x200603b 359 #define MASK_REMW 0xfe00707f 360 #define MATCH_REMUW 0x200703b 361 #define MASK_REMUW 0xfe00707f 362 #define MATCH_AMOADD_W 0x202f 363 #define MASK_AMOADD_W 0xf800707f 364 #define MATCH_AMOXOR_W 0x2000202f 365 #define MASK_AMOXOR_W 0xf800707f 366 #define MATCH_AMOOR_W 0x4000202f 367 #define MASK_AMOOR_W 0xf800707f 368 #define MATCH_AMOAND_W 0x6000202f 369 #define MASK_AMOAND_W 0xf800707f 370 #define MATCH_AMOMIN_W 0x8000202f 371 #define MASK_AMOMIN_W 0xf800707f 372 #define MATCH_AMOMAX_W 0xa000202f 373 #define MASK_AMOMAX_W 0xf800707f 374 #define MATCH_AMOMINU_W 0xc000202f 375 #define MASK_AMOMINU_W 0xf800707f 376 #define MATCH_AMOMAXU_W 0xe000202f 377 #define MASK_AMOMAXU_W 0xf800707f 378 #define MATCH_AMOSWAP_W 0x800202f 379 #define MASK_AMOSWAP_W 0xf800707f 380 #define MATCH_LR_W 0x1000202f 381 #define MASK_LR_W 0xf9f0707f 382 #define MATCH_SC_W 0x1800202f 383 #define MASK_SC_W 0xf800707f 384 #define MATCH_AMOADD_D 0x302f 385 #define MASK_AMOADD_D 0xf800707f 386 #define MATCH_AMOXOR_D 0x2000302f 387 #define MASK_AMOXOR_D 0xf800707f 388 #define MATCH_AMOOR_D 0x4000302f 389 #define MASK_AMOOR_D 0xf800707f 390 #define MATCH_AMOAND_D 0x6000302f 391 #define MASK_AMOAND_D 0xf800707f 392 #define MATCH_AMOMIN_D 0x8000302f 393 #define MASK_AMOMIN_D 0xf800707f 394 #define MATCH_AMOMAX_D 0xa000302f 395 #define MASK_AMOMAX_D 0xf800707f 396 #define MATCH_AMOMINU_D 0xc000302f 397 #define MASK_AMOMINU_D 0xf800707f 398 #define MATCH_AMOMAXU_D 0xe000302f 399 #define MASK_AMOMAXU_D 0xf800707f 400 #define MATCH_AMOSWAP_D 0x800302f 401 #define MASK_AMOSWAP_D 0xf800707f 402 #define MATCH_LR_D 0x1000302f 403 #define MASK_LR_D 0xf9f0707f 404 #define MATCH_SC_D 0x1800302f 405 #define MASK_SC_D 0xf800707f 406 #define MATCH_ECALL 0x73 407 #define MASK_ECALL 0xffffffff 408 #define MATCH_EBREAK 0x100073 409 #define MASK_EBREAK 0xffffffff 410 #define MATCH_URET 0x200073 411 #define MASK_URET 0xffffffff 412 #define MATCH_SRET 0x10200073 413 #define MASK_SRET 0xffffffff 414 #define MATCH_HRET 0x20200073 415 #define MASK_HRET 0xffffffff 416 #define MATCH_MRET 0x30200073 417 #define MASK_MRET 0xffffffff 418 #define MATCH_DRET 0x7b200073 419 #define MASK_DRET 0xffffffff 420 #define MATCH_SFENCE_VM 0x10400073 421 #define MASK_SFENCE_VM 0xfff07fff 422 #define MATCH_WFI 0x10500073 423 #define MASK_WFI 0xffffffff 424 #define MATCH_CSRRW 0x1073 425 #define MASK_CSRRW 0x707f 426 #define MATCH_CSRRS 0x2073 427 #define MASK_CSRRS 0x707f 428 #define MATCH_CSRRC 0x3073 429 #define MASK_CSRRC 0x707f 430 #define MATCH_CSRRWI 0x5073 431 #define MASK_CSRRWI 0x707f 432 #define MATCH_CSRRSI 0x6073 433 #define MASK_CSRRSI 0x707f 434 #define MATCH_CSRRCI 0x7073 435 #define MASK_CSRRCI 0x707f 436 #define MATCH_FADD_S 0x53 437 #define MASK_FADD_S 0xfe00007f 438 #define MATCH_FSUB_S 0x8000053 439 #define MASK_FSUB_S 0xfe00007f 440 #define MATCH_FMUL_S 0x10000053 441 #define MASK_FMUL_S 0xfe00007f 442 #define MATCH_FDIV_S 0x18000053 443 #define MASK_FDIV_S 0xfe00007f 444 #define MATCH_FSGNJ_S 0x20000053 445 #define MASK_FSGNJ_S 0xfe00707f 446 #define MATCH_FSGNJN_S 0x20001053 447 #define MASK_FSGNJN_S 0xfe00707f 448 #define MATCH_FSGNJX_S 0x20002053 449 #define MASK_FSGNJX_S 0xfe00707f 450 #define MATCH_FMIN_S 0x28000053 451 #define MASK_FMIN_S 0xfe00707f 452 #define MATCH_FMAX_S 0x28001053 453 #define MASK_FMAX_S 0xfe00707f 454 #define MATCH_FSQRT_S 0x58000053 455 #define MASK_FSQRT_S 0xfff0007f 456 #define MATCH_FADD_D 0x2000053 457 #define MASK_FADD_D 0xfe00007f 458 #define MATCH_FSUB_D 0xa000053 459 #define MASK_FSUB_D 0xfe00007f 460 #define MATCH_FMUL_D 0x12000053 461 #define MASK_FMUL_D 0xfe00007f 462 #define MATCH_FDIV_D 0x1a000053 463 #define MASK_FDIV_D 0xfe00007f 464 #define MATCH_FSGNJ_D 0x22000053 465 #define MASK_FSGNJ_D 0xfe00707f 466 #define MATCH_FSGNJN_D 0x22001053 467 #define MASK_FSGNJN_D 0xfe00707f 468 #define MATCH_FSGNJX_D 0x22002053 469 #define MASK_FSGNJX_D 0xfe00707f 470 #define MATCH_FMIN_D 0x2a000053 471 #define MASK_FMIN_D 0xfe00707f 472 #define MATCH_FMAX_D 0x2a001053 473 #define MASK_FMAX_D 0xfe00707f 474 #define MATCH_FCVT_S_D 0x40100053 475 #define MASK_FCVT_S_D 0xfff0007f 476 #define MATCH_FCVT_D_S 0x42000053 477 #define MASK_FCVT_D_S 0xfff0007f 478 #define MATCH_FSQRT_D 0x5a000053 479 #define MASK_FSQRT_D 0xfff0007f 480 #define MATCH_FLE_S 0xa0000053 481 #define MASK_FLE_S 0xfe00707f 482 #define MATCH_FLT_S 0xa0001053 483 #define MASK_FLT_S 0xfe00707f 484 #define MATCH_FEQ_S 0xa0002053 485 #define MASK_FEQ_S 0xfe00707f 486 #define MATCH_FLE_D 0xa2000053 487 #define MASK_FLE_D 0xfe00707f 488 #define MATCH_FLT_D 0xa2001053 489 #define MASK_FLT_D 0xfe00707f 490 #define MATCH_FEQ_D 0xa2002053 491 #define MASK_FEQ_D 0xfe00707f 492 #define MATCH_FCVT_W_S 0xc0000053 493 #define MASK_FCVT_W_S 0xfff0007f 494 #define MATCH_FCVT_WU_S 0xc0100053 495 #define MASK_FCVT_WU_S 0xfff0007f 496 #define MATCH_FCVT_L_S 0xc0200053 497 #define MASK_FCVT_L_S 0xfff0007f 498 #define MATCH_FCVT_LU_S 0xc0300053 499 #define MASK_FCVT_LU_S 0xfff0007f 500 #define MATCH_FMV_X_S 0xe0000053 501 #define MASK_FMV_X_S 0xfff0707f 502 #define MATCH_FCLASS_S 0xe0001053 503 #define MASK_FCLASS_S 0xfff0707f 504 #define MATCH_FCVT_W_D 0xc2000053 505 #define MASK_FCVT_W_D 0xfff0007f 506 #define MATCH_FCVT_WU_D 0xc2100053 507 #define MASK_FCVT_WU_D 0xfff0007f 508 #define MATCH_FCVT_L_D 0xc2200053 509 #define MASK_FCVT_L_D 0xfff0007f 510 #define MATCH_FCVT_LU_D 0xc2300053 511 #define MASK_FCVT_LU_D 0xfff0007f 512 #define MATCH_FMV_X_D 0xe2000053 513 #define MASK_FMV_X_D 0xfff0707f 514 #define MATCH_FCLASS_D 0xe2001053 515 #define MASK_FCLASS_D 0xfff0707f 516 #define MATCH_FCVT_S_W 0xd0000053 517 #define MASK_FCVT_S_W 0xfff0007f 518 #define MATCH_FCVT_S_WU 0xd0100053 519 #define MASK_FCVT_S_WU 0xfff0007f 520 #define MATCH_FCVT_S_L 0xd0200053 521 #define MASK_FCVT_S_L 0xfff0007f 522 #define MATCH_FCVT_S_LU 0xd0300053 523 #define MASK_FCVT_S_LU 0xfff0007f 524 #define MATCH_FMV_S_X 0xf0000053 525 #define MASK_FMV_S_X 0xfff0707f 526 #define MATCH_FCVT_D_W 0xd2000053 527 #define MASK_FCVT_D_W 0xfff0007f 528 #define MATCH_FCVT_D_WU 0xd2100053 529 #define MASK_FCVT_D_WU 0xfff0007f 530 #define MATCH_FCVT_D_L 0xd2200053 531 #define MASK_FCVT_D_L 0xfff0007f 532 #define MATCH_FCVT_D_LU 0xd2300053 533 #define MASK_FCVT_D_LU 0xfff0007f 534 #define MATCH_FMV_D_X 0xf2000053 535 #define MASK_FMV_D_X 0xfff0707f 536 #define MATCH_FLW 0x2007 537 #define MASK_FLW 0x707f 538 #define MATCH_FLD 0x3007 539 #define MASK_FLD 0x707f 540 #define MATCH_FSW 0x2027 541 #define MASK_FSW 0x707f 542 #define MATCH_FSD 0x3027 543 #define MASK_FSD 0x707f 544 #define MATCH_FMADD_S 0x43 545 #define MASK_FMADD_S 0x600007f 546 #define MATCH_FMSUB_S 0x47 547 #define MASK_FMSUB_S 0x600007f 548 #define MATCH_FNMSUB_S 0x4b 549 #define MASK_FNMSUB_S 0x600007f 550 #define MATCH_FNMADD_S 0x4f 551 #define MASK_FNMADD_S 0x600007f 552 #define MATCH_FMADD_D 0x2000043 553 #define MASK_FMADD_D 0x600007f 554 #define MATCH_FMSUB_D 0x2000047 555 #define MASK_FMSUB_D 0x600007f 556 #define MATCH_FNMSUB_D 0x200004b 557 #define MASK_FNMSUB_D 0x600007f 558 #define MATCH_FNMADD_D 0x200004f 559 #define MASK_FNMADD_D 0x600007f 560 #define MATCH_C_NOP 0x1 561 #define MASK_C_NOP 0xffff 562 #define MATCH_C_ADDI16SP 0x6101 563 #define MASK_C_ADDI16SP 0xef83 564 #define MATCH_C_JR 0x8002 565 #define MASK_C_JR 0xf07f 566 #define MATCH_C_JALR 0x9002 567 #define MASK_C_JALR 0xf07f 568 #define MATCH_C_EBREAK 0x9002 569 #define MASK_C_EBREAK 0xffff 570 #define MATCH_C_LD 0x6000 571 #define MASK_C_LD 0xe003 572 #define MATCH_C_SD 0xe000 573 #define MASK_C_SD 0xe003 574 #define MATCH_C_ADDIW 0x2001 575 #define MASK_C_ADDIW 0xe003 576 #define MATCH_C_LDSP 0x6002 577 #define MASK_C_LDSP 0xe003 578 #define MATCH_C_SDSP 0xe002 579 #define MASK_C_SDSP 0xe003 580 #define MATCH_C_ADDI4SPN 0x0 581 #define MASK_C_ADDI4SPN 0xe003 582 #define MATCH_C_FLD 0x2000 583 #define MASK_C_FLD 0xe003 584 #define MATCH_C_LW 0x4000 585 #define MASK_C_LW 0xe003 586 #define MATCH_C_FLW 0x6000 587 #define MASK_C_FLW 0xe003 588 #define MATCH_C_FSD 0xa000 589 #define MASK_C_FSD 0xe003 590 #define MATCH_C_SW 0xc000 591 #define MASK_C_SW 0xe003 592 #define MATCH_C_FSW 0xe000 593 #define MASK_C_FSW 0xe003 594 #define MATCH_C_ADDI 0x1 595 #define MASK_C_ADDI 0xe003 596 #define MATCH_C_JAL 0x2001 597 #define MASK_C_JAL 0xe003 598 #define MATCH_C_LI 0x4001 599 #define MASK_C_LI 0xe003 600 #define MATCH_C_LUI 0x6001 601 #define MASK_C_LUI 0xe003 602 #define MATCH_C_SRLI 0x8001 603 #define MASK_C_SRLI 0xec03 604 #define MATCH_C_SRAI 0x8401 605 #define MASK_C_SRAI 0xec03 606 #define MATCH_C_ANDI 0x8801 607 #define MASK_C_ANDI 0xec03 608 #define MATCH_C_SUB 0x8c01 609 #define MASK_C_SUB 0xfc63 610 #define MATCH_C_XOR 0x8c21 611 #define MASK_C_XOR 0xfc63 612 #define MATCH_C_OR 0x8c41 613 #define MASK_C_OR 0xfc63 614 #define MATCH_C_AND 0x8c61 615 #define MASK_C_AND 0xfc63 616 #define MATCH_C_SUBW 0x9c01 617 #define MASK_C_SUBW 0xfc63 618 #define MATCH_C_ADDW 0x9c21 619 #define MASK_C_ADDW 0xfc63 620 #define MATCH_C_J 0xa001 621 #define MASK_C_J 0xe003 622 #define MATCH_C_BEQZ 0xc001 623 #define MASK_C_BEQZ 0xe003 624 #define MATCH_C_BNEZ 0xe001 625 #define MASK_C_BNEZ 0xe003 626 #define MATCH_C_SLLI 0x2 627 #define MASK_C_SLLI 0xe003 628 #define MATCH_C_FLDSP 0x2002 629 #define MASK_C_FLDSP 0xe003 630 #define MATCH_C_LWSP 0x4002 631 #define MASK_C_LWSP 0xe003 632 #define MATCH_C_FLWSP 0x6002 633 #define MASK_C_FLWSP 0xe003 634 #define MATCH_C_MV 0x8002 635 #define MASK_C_MV 0xf003 636 #define MATCH_C_ADD 0x9002 637 #define MASK_C_ADD 0xf003 638 #define MATCH_C_FSDSP 0xa002 639 #define MASK_C_FSDSP 0xe003 640 #define MATCH_C_SWSP 0xc002 641 #define MASK_C_SWSP 0xe003 642 #define MATCH_C_FSWSP 0xe002 643 #define MASK_C_FSWSP 0xe003 644 #define MATCH_CUSTOM0 0xb 645 #define MASK_CUSTOM0 0x707f 646 #define MATCH_CUSTOM0_RS1 0x200b 647 #define MASK_CUSTOM0_RS1 0x707f 648 #define MATCH_CUSTOM0_RS1_RS2 0x300b 649 #define MASK_CUSTOM0_RS1_RS2 0x707f 650 #define MATCH_CUSTOM0_RD 0x400b 651 #define MASK_CUSTOM0_RD 0x707f 652 #define MATCH_CUSTOM0_RD_RS1 0x600b 653 #define MASK_CUSTOM0_RD_RS1 0x707f 654 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 655 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f 656 #define MATCH_CUSTOM1 0x2b 657 #define MASK_CUSTOM1 0x707f 658 #define MATCH_CUSTOM1_RS1 0x202b 659 #define MASK_CUSTOM1_RS1 0x707f 660 #define MATCH_CUSTOM1_RS1_RS2 0x302b 661 #define MASK_CUSTOM1_RS1_RS2 0x707f 662 #define MATCH_CUSTOM1_RD 0x402b 663 #define MASK_CUSTOM1_RD 0x707f 664 #define MATCH_CUSTOM1_RD_RS1 0x602b 665 #define MASK_CUSTOM1_RD_RS1 0x707f 666 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 667 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f 668 #define MATCH_CUSTOM2 0x5b 669 #define MASK_CUSTOM2 0x707f 670 #define MATCH_CUSTOM2_RS1 0x205b 671 #define MASK_CUSTOM2_RS1 0x707f 672 #define MATCH_CUSTOM2_RS1_RS2 0x305b 673 #define MASK_CUSTOM2_RS1_RS2 0x707f 674 #define MATCH_CUSTOM2_RD 0x405b 675 #define MASK_CUSTOM2_RD 0x707f 676 #define MATCH_CUSTOM2_RD_RS1 0x605b 677 #define MASK_CUSTOM2_RD_RS1 0x707f 678 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 679 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f 680 #define MATCH_CUSTOM3 0x7b 681 #define MASK_CUSTOM3 0x707f 682 #define MATCH_CUSTOM3_RS1 0x207b 683 #define MASK_CUSTOM3_RS1 0x707f 684 #define MATCH_CUSTOM3_RS1_RS2 0x307b 685 #define MASK_CUSTOM3_RS1_RS2 0x707f 686 #define MATCH_CUSTOM3_RD 0x407b 687 #define MASK_CUSTOM3_RD 0x707f 688 #define MATCH_CUSTOM3_RD_RS1 0x607b 689 #define MASK_CUSTOM3_RD_RS1 0x707f 690 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 691 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f 692 #define CSR_FFLAGS 0x1 693 #define CSR_FRM 0x2 694 #define CSR_FCSR 0x3 695 #define CSR_CYCLE 0xc00 696 #define CSR_TIME 0xc01 697 #define CSR_INSTRET 0xc02 698 #define CSR_HPMCOUNTER3 0xc03 699 #define CSR_HPMCOUNTER4 0xc04 700 #define CSR_HPMCOUNTER5 0xc05 701 #define CSR_HPMCOUNTER6 0xc06 702 #define CSR_HPMCOUNTER7 0xc07 703 #define CSR_HPMCOUNTER8 0xc08 704 #define CSR_HPMCOUNTER9 0xc09 705 #define CSR_HPMCOUNTER10 0xc0a 706 #define CSR_HPMCOUNTER11 0xc0b 707 #define CSR_HPMCOUNTER12 0xc0c 708 #define CSR_HPMCOUNTER13 0xc0d 709 #define CSR_HPMCOUNTER14 0xc0e 710 #define CSR_HPMCOUNTER15 0xc0f 711 #define CSR_HPMCOUNTER16 0xc10 712 #define CSR_HPMCOUNTER17 0xc11 713 #define CSR_HPMCOUNTER18 0xc12 714 #define CSR_HPMCOUNTER19 0xc13 715 #define CSR_HPMCOUNTER20 0xc14 716 #define CSR_HPMCOUNTER21 0xc15 717 #define CSR_HPMCOUNTER22 0xc16 718 #define CSR_HPMCOUNTER23 0xc17 719 #define CSR_HPMCOUNTER24 0xc18 720 #define CSR_HPMCOUNTER25 0xc19 721 #define CSR_HPMCOUNTER26 0xc1a 722 #define CSR_HPMCOUNTER27 0xc1b 723 #define CSR_HPMCOUNTER28 0xc1c 724 #define CSR_HPMCOUNTER29 0xc1d 725 #define CSR_HPMCOUNTER30 0xc1e 726 #define CSR_HPMCOUNTER31 0xc1f 727 #define CSR_SSTATUS 0x100 728 #define CSR_SIE 0x104 729 #define CSR_STVEC 0x105 730 #define CSR_SSCRATCH 0x140 731 #define CSR_SEPC 0x141 732 #define CSR_SCAUSE 0x142 733 #define CSR_SBADADDR 0x143 734 #define CSR_SIP 0x144 735 #define CSR_SPTBR 0x180 736 #define CSR_MSTATUS 0x300 737 #define CSR_MISA 0x301 738 #define CSR_MEDELEG 0x302 739 #define CSR_MIDELEG 0x303 740 #define CSR_MIE 0x304 741 #define CSR_MTVEC 0x305 742 #define CSR_MCOUNTEREN 0x306 743 #define CSR_MSCRATCH 0x340 744 #define CSR_MEPC 0x341 745 #define CSR_MCAUSE 0x342 746 #define CSR_MBADADDR 0x343 747 #define CSR_MIP 0x344 748 #define CSR_TSELECT 0x7a0 749 #define CSR_TDATA1 0x7a1 750 #define CSR_TDATA2 0x7a2 751 #define CSR_TDATA3 0x7a3 752 #define CSR_DCSR 0x7b0 753 #define CSR_DPC 0x7b1 754 #define CSR_DSCRATCH 0x7b2 755 #define CSR_MCYCLE 0xb00 756 #define CSR_MINSTRET 0xb02 757 #define CSR_MHPMCOUNTER3 0xb03 758 #define CSR_MHPMCOUNTER4 0xb04 759 #define CSR_MHPMCOUNTER5 0xb05 760 #define CSR_MHPMCOUNTER6 0xb06 761 #define CSR_MHPMCOUNTER7 0xb07 762 #define CSR_MHPMCOUNTER8 0xb08 763 #define CSR_MHPMCOUNTER9 0xb09 764 #define CSR_MHPMCOUNTER10 0xb0a 765 #define CSR_MHPMCOUNTER11 0xb0b 766 #define CSR_MHPMCOUNTER12 0xb0c 767 #define CSR_MHPMCOUNTER13 0xb0d 768 #define CSR_MHPMCOUNTER14 0xb0e 769 #define CSR_MHPMCOUNTER15 0xb0f 770 #define CSR_MHPMCOUNTER16 0xb10 771 #define CSR_MHPMCOUNTER17 0xb11 772 #define CSR_MHPMCOUNTER18 0xb12 773 #define CSR_MHPMCOUNTER19 0xb13 774 #define CSR_MHPMCOUNTER20 0xb14 775 #define CSR_MHPMCOUNTER21 0xb15 776 #define CSR_MHPMCOUNTER22 0xb16 777 #define CSR_MHPMCOUNTER23 0xb17 778 #define CSR_MHPMCOUNTER24 0xb18 779 #define CSR_MHPMCOUNTER25 0xb19 780 #define CSR_MHPMCOUNTER26 0xb1a 781 #define CSR_MHPMCOUNTER27 0xb1b 782 #define CSR_MHPMCOUNTER28 0xb1c 783 #define CSR_MHPMCOUNTER29 0xb1d 784 #define CSR_MHPMCOUNTER30 0xb1e 785 #define CSR_MHPMCOUNTER31 0xb1f 786 #define CSR_MUCOUNTEREN 0x320 787 #define CSR_MSCOUNTEREN 0x321 788 #define CSR_MHPMEVENT3 0x323 789 #define CSR_MHPMEVENT4 0x324 790 #define CSR_MHPMEVENT5 0x325 791 #define CSR_MHPMEVENT6 0x326 792 #define CSR_MHPMEVENT7 0x327 793 #define CSR_MHPMEVENT8 0x328 794 #define CSR_MHPMEVENT9 0x329 795 #define CSR_MHPMEVENT10 0x32a 796 #define CSR_MHPMEVENT11 0x32b 797 #define CSR_MHPMEVENT12 0x32c 798 #define CSR_MHPMEVENT13 0x32d 799 #define CSR_MHPMEVENT14 0x32e 800 #define CSR_MHPMEVENT15 0x32f 801 #define CSR_MHPMEVENT16 0x330 802 #define CSR_MHPMEVENT17 0x331 803 #define CSR_MHPMEVENT18 0x332 804 #define CSR_MHPMEVENT19 0x333 805 #define CSR_MHPMEVENT20 0x334 806 #define CSR_MHPMEVENT21 0x335 807 #define CSR_MHPMEVENT22 0x336 808 #define CSR_MHPMEVENT23 0x337 809 #define CSR_MHPMEVENT24 0x338 810 #define CSR_MHPMEVENT25 0x339 811 #define CSR_MHPMEVENT26 0x33a 812 #define CSR_MHPMEVENT27 0x33b 813 #define CSR_MHPMEVENT28 0x33c 814 #define CSR_MHPMEVENT29 0x33d 815 #define CSR_MHPMEVENT30 0x33e 816 #define CSR_MHPMEVENT31 0x33f 817 #define CSR_MVENDORID 0xf11 818 #define CSR_MARCHID 0xf12 819 #define CSR_MIMPID 0xf13 820 #define CSR_MHARTID 0xf14 821 #define CSR_CYCLEH 0xc80 822 #define CSR_TIMEH 0xc81 823 #define CSR_INSTRETH 0xc82 824 #define CSR_HPMCOUNTER3H 0xc83 825 #define CSR_HPMCOUNTER4H 0xc84 826 #define CSR_HPMCOUNTER5H 0xc85 827 #define CSR_HPMCOUNTER6H 0xc86 828 #define CSR_HPMCOUNTER7H 0xc87 829 #define CSR_HPMCOUNTER8H 0xc88 830 #define CSR_HPMCOUNTER9H 0xc89 831 #define CSR_HPMCOUNTER10H 0xc8a 832 #define CSR_HPMCOUNTER11H 0xc8b 833 #define CSR_HPMCOUNTER12H 0xc8c 834 #define CSR_HPMCOUNTER13H 0xc8d 835 #define CSR_HPMCOUNTER14H 0xc8e 836 #define CSR_HPMCOUNTER15H 0xc8f 837 #define CSR_HPMCOUNTER16H 0xc90 838 #define CSR_HPMCOUNTER17H 0xc91 839 #define CSR_HPMCOUNTER18H 0xc92 840 #define CSR_HPMCOUNTER19H 0xc93 841 #define CSR_HPMCOUNTER20H 0xc94 842 #define CSR_HPMCOUNTER21H 0xc95 843 #define CSR_HPMCOUNTER22H 0xc96 844 #define CSR_HPMCOUNTER23H 0xc97 845 #define CSR_HPMCOUNTER24H 0xc98 846 #define CSR_HPMCOUNTER25H 0xc99 847 #define CSR_HPMCOUNTER26H 0xc9a 848 #define CSR_HPMCOUNTER27H 0xc9b 849 #define CSR_HPMCOUNTER28H 0xc9c 850 #define CSR_HPMCOUNTER29H 0xc9d 851 #define CSR_HPMCOUNTER30H 0xc9e 852 #define CSR_HPMCOUNTER31H 0xc9f 853 #define CSR_MCYCLEH 0xb80 854 #define CSR_MINSTRETH 0xb82 855 #define CSR_MHPMCOUNTER3H 0xb83 856 #define CSR_MHPMCOUNTER4H 0xb84 857 #define CSR_MHPMCOUNTER5H 0xb85 858 #define CSR_MHPMCOUNTER6H 0xb86 859 #define CSR_MHPMCOUNTER7H 0xb87 860 #define CSR_MHPMCOUNTER8H 0xb88 861 #define CSR_MHPMCOUNTER9H 0xb89 862 #define CSR_MHPMCOUNTER10H 0xb8a 863 #define CSR_MHPMCOUNTER11H 0xb8b 864 #define CSR_MHPMCOUNTER12H 0xb8c 865 #define CSR_MHPMCOUNTER13H 0xb8d 866 #define CSR_MHPMCOUNTER14H 0xb8e 867 #define CSR_MHPMCOUNTER15H 0xb8f 868 #define CSR_MHPMCOUNTER16H 0xb90 869 #define CSR_MHPMCOUNTER17H 0xb91 870 #define CSR_MHPMCOUNTER18H 0xb92 871 #define CSR_MHPMCOUNTER19H 0xb93 872 #define CSR_MHPMCOUNTER20H 0xb94 873 #define CSR_MHPMCOUNTER21H 0xb95 874 #define CSR_MHPMCOUNTER22H 0xb96 875 #define CSR_MHPMCOUNTER23H 0xb97 876 #define CSR_MHPMCOUNTER24H 0xb98 877 #define CSR_MHPMCOUNTER25H 0xb99 878 #define CSR_MHPMCOUNTER26H 0xb9a 879 #define CSR_MHPMCOUNTER27H 0xb9b 880 #define CSR_MHPMCOUNTER28H 0xb9c 881 #define CSR_MHPMCOUNTER29H 0xb9d 882 #define CSR_MHPMCOUNTER30H 0xb9e 883 #define CSR_MHPMCOUNTER31H 0xb9f 884 885 886 #define CSR_MTVT 0x307 887 #define CSR_MNXTI 0x345 888 889 #define CSR_MCOUNTINHIBIT 0x320 890 891 #define CSR_MNVEC 0x7C3 892 893 #define CSR_MTVT2 0x7EC 894 #define CSR_JALMNXTI 0x7ED 895 #define CSR_PUSHMCAUSE 0x7EE 896 #define CSR_PUSHMEPC 0x7EF 897 #define CSR_PUSHMSUBM 0x7EB 898 899 #define CSR_WFE 0x810 900 #define CSR_SLEEPVALUE 0x811 901 #define CSR_TXEVT 0x812 902 903 #define CSR_MMISC_CTL 0x7d0 904 #define CSR_MSUBM 0x7c4 905 906 907 #define CAUSE_MISALIGNED_FETCH 0x0 908 #define CAUSE_FAULT_FETCH 0x1 909 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 910 #define CAUSE_BREAKPOINT 0x3 911 #define CAUSE_MISALIGNED_LOAD 0x4 912 #define CAUSE_FAULT_LOAD 0x5 913 #define CAUSE_MISALIGNED_STORE 0x6 914 #define CAUSE_FAULT_STORE 0x7 915 #define CAUSE_USER_ECALL 0x8 916 #define CAUSE_SUPERVISOR_ECALL 0x9 917 #define CAUSE_HYPERVISOR_ECALL 0xa 918 #define CAUSE_MACHINE_ECALL 0xb 919 #endif 920 #ifdef DECLARE_INSN 921 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 922 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 923 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 924 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 925 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 926 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 927 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 928 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 929 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 930 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 931 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 932 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 933 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 934 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 935 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 936 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 937 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 938 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 939 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 940 DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 941 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 942 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 943 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 944 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 945 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 946 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 947 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 948 DECLARE_INSN(or, MATCH_OR, MASK_OR) 949 DECLARE_INSN(and, MATCH_AND, MASK_AND) 950 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 951 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 952 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 953 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 954 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 955 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 956 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 957 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 958 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 959 DECLARE_INSN(lb, MATCH_LB, MASK_LB) 960 DECLARE_INSN(lh, MATCH_LH, MASK_LH) 961 DECLARE_INSN(lw, MATCH_LW, MASK_LW) 962 DECLARE_INSN(ld, MATCH_LD, MASK_LD) 963 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 964 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 965 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 966 DECLARE_INSN(sb, MATCH_SB, MASK_SB) 967 DECLARE_INSN(sh, MATCH_SH, MASK_SH) 968 DECLARE_INSN(sw, MATCH_SW, MASK_SW) 969 DECLARE_INSN(sd, MATCH_SD, MASK_SD) 970 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 971 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 972 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 973 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 974 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 975 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 976 DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 977 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 978 DECLARE_INSN(rem, MATCH_REM, MASK_REM) 979 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 980 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 981 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 982 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 983 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 984 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 985 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 986 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 987 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 988 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 989 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 990 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 991 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 992 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 993 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 994 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 995 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 996 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 997 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 998 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 999 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 1000 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 1001 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 1002 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 1003 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 1004 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 1005 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 1006 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 1007 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 1008 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 1009 DECLARE_INSN(uret, MATCH_URET, MASK_URET) 1010 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 1011 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) 1012 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 1013 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 1014 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) 1015 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 1016 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 1017 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 1018 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 1019 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 1020 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 1021 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 1022 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 1023 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 1024 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 1025 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 1026 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 1027 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 1028 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 1029 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 1030 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 1031 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 1032 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 1033 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 1034 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 1035 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 1036 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 1037 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 1038 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 1039 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 1040 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 1041 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 1042 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 1043 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 1044 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 1045 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 1046 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 1047 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 1048 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 1049 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 1050 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 1051 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 1052 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 1053 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 1054 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) 1055 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 1056 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 1057 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 1058 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 1059 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 1060 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 1061 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 1062 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 1063 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 1064 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 1065 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 1066 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) 1067 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 1068 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 1069 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 1070 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 1071 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 1072 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 1073 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 1074 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 1075 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 1076 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 1077 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 1078 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 1079 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 1080 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 1081 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 1082 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 1083 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 1084 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 1085 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 1086 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 1087 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 1088 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 1089 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 1090 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 1091 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 1092 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 1093 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 1094 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 1095 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 1096 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 1097 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 1098 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 1099 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 1100 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 1101 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 1102 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 1103 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 1104 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 1105 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 1106 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 1107 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 1108 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 1109 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 1110 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 1111 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 1112 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 1113 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 1114 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 1115 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 1116 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 1117 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 1118 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 1119 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 1120 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 1121 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 1122 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 1123 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 1124 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 1125 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 1126 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 1127 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 1128 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 1129 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 1130 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 1131 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, 1132 MASK_CUSTOM0_RD_RS1_RS2) 1133 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 1134 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 1135 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 1136 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 1137 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 1138 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, 1139 MASK_CUSTOM1_RD_RS1_RS2) 1140 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 1141 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 1142 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 1143 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 1144 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 1145 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, 1146 MASK_CUSTOM2_RD_RS1_RS2) 1147 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 1148 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 1149 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 1150 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 1151 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 1152 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, 1153 MASK_CUSTOM3_RD_RS1_RS2) 1154 #endif 1155 #ifdef DECLARE_CSR 1156 DECLARE_CSR(fflags, CSR_FFLAGS) 1157 DECLARE_CSR(frm, CSR_FRM) 1158 DECLARE_CSR(fcsr, CSR_FCSR) 1159 DECLARE_CSR(cycle, CSR_CYCLE) 1160 DECLARE_CSR(time, CSR_TIME) 1161 DECLARE_CSR(instret, CSR_INSTRET) 1162 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 1163 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 1164 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 1165 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 1166 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 1167 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 1168 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 1169 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 1170 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 1171 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 1172 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 1173 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 1174 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 1175 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 1176 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 1177 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 1178 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 1179 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 1180 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 1181 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 1182 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 1183 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 1184 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 1185 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 1186 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 1187 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 1188 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 1189 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 1190 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 1191 DECLARE_CSR(sstatus, CSR_SSTATUS) 1192 DECLARE_CSR(sie, CSR_SIE) 1193 DECLARE_CSR(stvec, CSR_STVEC) 1194 DECLARE_CSR(sscratch, CSR_SSCRATCH) 1195 DECLARE_CSR(sepc, CSR_SEPC) 1196 DECLARE_CSR(scause, CSR_SCAUSE) 1197 DECLARE_CSR(sbadaddr, CSR_SBADADDR) 1198 DECLARE_CSR(sip, CSR_SIP) 1199 DECLARE_CSR(sptbr, CSR_SPTBR) 1200 DECLARE_CSR(mstatus, CSR_MSTATUS) 1201 DECLARE_CSR(misa, CSR_MISA) 1202 DECLARE_CSR(medeleg, CSR_MEDELEG) 1203 DECLARE_CSR(mideleg, CSR_MIDELEG) 1204 DECLARE_CSR(mie, CSR_MIE) 1205 DECLARE_CSR(mtvec, CSR_MTVEC) 1206 DECLARE_CSR(mscratch, CSR_MSCRATCH) 1207 DECLARE_CSR(mepc, CSR_MEPC) 1208 DECLARE_CSR(mcause, CSR_MCAUSE) 1209 DECLARE_CSR(mbadaddr, CSR_MBADADDR) 1210 DECLARE_CSR(mip, CSR_MIP) 1211 DECLARE_CSR(tselect, CSR_TSELECT) 1212 DECLARE_CSR(tdata1, CSR_TDATA1) 1213 DECLARE_CSR(tdata2, CSR_TDATA2) 1214 DECLARE_CSR(tdata3, CSR_TDATA3) 1215 DECLARE_CSR(dcsr, CSR_DCSR) 1216 DECLARE_CSR(dpc, CSR_DPC) 1217 DECLARE_CSR(dscratch, CSR_DSCRATCH) 1218 DECLARE_CSR(mcycle, CSR_MCYCLE) 1219 DECLARE_CSR(minstret, CSR_MINSTRET) 1220 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 1221 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 1222 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 1223 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 1224 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 1225 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 1226 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 1227 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 1228 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 1229 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 1230 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 1231 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 1232 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 1233 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 1234 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 1235 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 1236 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 1237 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 1238 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 1239 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 1240 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 1241 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 1242 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 1243 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 1244 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 1245 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 1246 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 1247 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 1248 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 1249 DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) 1250 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) 1251 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 1252 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 1253 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 1254 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 1255 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 1256 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 1257 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 1258 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 1259 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 1260 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 1261 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 1262 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 1263 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 1264 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 1265 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 1266 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 1267 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 1268 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 1269 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 1270 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 1271 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 1272 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 1273 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 1274 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 1275 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 1276 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 1277 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 1278 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 1279 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 1280 DECLARE_CSR(mvendorid, CSR_MVENDORID) 1281 DECLARE_CSR(marchid, CSR_MARCHID) 1282 DECLARE_CSR(mimpid, CSR_MIMPID) 1283 DECLARE_CSR(mhartid, CSR_MHARTID) 1284 DECLARE_CSR(cycleh, CSR_CYCLEH) 1285 DECLARE_CSR(timeh, CSR_TIMEH) 1286 DECLARE_CSR(instreth, CSR_INSTRETH) 1287 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 1288 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 1289 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 1290 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 1291 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 1292 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 1293 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 1294 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 1295 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 1296 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 1297 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 1298 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 1299 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 1300 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 1301 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 1302 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 1303 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 1304 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 1305 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 1306 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 1307 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 1308 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 1309 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 1310 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 1311 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 1312 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 1313 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 1314 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 1315 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 1316 DECLARE_CSR(mcycleh, CSR_MCYCLEH) 1317 DECLARE_CSR(minstreth, CSR_MINSTRETH) 1318 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 1319 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 1320 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 1321 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 1322 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 1323 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 1324 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 1325 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 1326 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 1327 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 1328 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 1329 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 1330 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 1331 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 1332 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 1333 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 1334 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 1335 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 1336 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 1337 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 1338 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 1339 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 1340 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 1341 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 1342 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 1343 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 1344 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 1345 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 1346 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 1347 #endif 1348 #ifdef DECLARE_CAUSE 1349 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 1350 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) 1351 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 1352 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 1353 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 1354 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) 1355 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 1356 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) 1357 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 1358 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 1359 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) 1360 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 1361 #endif 1362 1363
