| /Zephyr-latest/soc/telink/tlsr/tlsr951x/ |
| D | start.S | 4 * SPDX-License-Identifier: Apache-2.0
34 /* Enable I/D-Cache */
36 ori t0, t0, 1 #/I-Cache
37 ori t0, t0, 2 #/D-Cache
41 /* Enable misaligned access and non-blocking load */
47 la t2, _AES_DATA_VMA_START
48 la t3, _AES_DATA_VMA_END
56 la t1, _RETENTION_DATA_LMA_START
57 la t2, _RETENTION_DATA_VMA_START
58 la t3, _RETENTION_DATA_VMA_END
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| /Zephyr-latest/arch/riscv/core/ |
| D | reset.S | 2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
37 * Remainder of asm-land initialization code before we can jump into
50 * Enable floating-point.
56 * Floating-point rounding mode set to IEEE-754 default, and clear
63 /* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
64 la t0, z_interrupt_stacks
81 la sp, z_interrupt_stacks
97 la t0, riscv_cpu_wake_flag
98 li t1, -1
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| D | pmp.S | 4 * SPDX-License-Identifier: Apache-2.0
31 * known (luckily they're all power-of-2's simplifying the code further).
39 la t0, pmpaddr_store
40 slli t1, a0, 4 /* 16-byte instruction blocks */
63 * a1 = (a1 + RV_REGSIZE - 1) / RV_REGSIZE
65 la t0, pmpcfg_store
67 slli t1, a0, 4 /* 16-byte instruction blocks */
69 addi a1, a1, RV_REGSIZE - 1
91 la t0, pmpcfg_zerotail
92 slli a0, a0, 2 /* 4-byte instruction blocks */
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| D | isr.S | 2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
6 * SPDX-License-Identifier: Apache-2.0
45 /* Convenience macro for storing callee saved register [s0 - s11] states. */
65 la \dst, _kernel + ___kernel_t_cpus_OFFSET
110 * Generic architecture-level IRQ handling, along with callouts to
111 * SoC-specific routines.
117 * Since RISC-V does not completely prescribe IRQ handling behavior,
122 * - __soc_is_irq (optional): decide if we're handling an interrupt or an
124 * - __soc_handle_irq: handle SoC-specific details for a pending IRQ
125 * (e.g. clear a pending bit in a SoC-specific register)
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| /Zephyr-latest/soc/common/riscv-privileged/ |
| D | vector.S | 2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
5 * SPDX-License-Identifier: Apache-2.0
24 la gp, __global_pointer$
45 la t0, _isr_wrapper
64 la t0, _irq_vector_table
72 * Set mtvec (Machine Trap-Vector Base-Address Register)
78 * NOTE: _irq_vector_table is 256-byte aligned. Incorrect alignment
81 la t0, _irq_vector_table /* Load address of interrupt vector table */
91 la t0, _isr_wrapper
100 * Set mtvec (Machine Trap-Vector Base-Address Register)
[all …]
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| /Zephyr-latest/arch/mips/core/ |
| D | reset.S | 4 * SPDX-License-Identifier: Apache-2.0
17 * Remainder of asm-land initialization code before we can jump into
33 /* Pre-populate all bytes in z_interrupt_stacks with 0xAA */
34 la t0, z_interrupt_stacks
50 la sp, __stack
55 la v0, z_prep_c
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| D | isr.S | 6 * SPDX-License-Identifier: Apache-2.0
61 addi sp, sp, -__struct_arch_esf_SIZEOF ;\
79 la k0, _mips_interrupt
85 * Save caller-saved registers on current thread stack.
146 * If NULL, jump to reschedule to perform a context-switch, otherwise,
149 la t0, _offload_routine
160 * Go to reschedule to handle context-switch
174 la k1, _kernel
180 addi sp, sp, -16
220 * Sometimes this code is execute back-to-back before the target thread
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| D | swap.S | 6 * SPDX-License-Identifier: Apache-2.0
31 la k0, _kernel
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| /Zephyr-latest/soc/ite/ec/common/ |
| D | vector.S | 5 * SPDX-License-Identifier: Apache-2.0
23 la gp, __global_pointer$
31 la t0, IT8XXX2_GCTRL_PMER3
36 la t0, IT8XXX2_JTAG_PINS_BASE
50 la t0, IT8XXX2_JTAG_VOLT_SET
55 * Set mtvec (Machine Trap-Vector Base-Address Register)
58 la t0, _isr_wrapper
63 * bit[3-0]@EIDSR=8: instruction local memory size is 1M byte
66 la t0, IT8XXX2_GCTRL_EIDSR
76 * eflash signature used to enable specific function after power-on reset.
[all …]
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| /Zephyr-latest/soc/gd/gd32/gd32vf103/ |
| D | entry.S | 4 * SPDX-License-Identifier: Apache-2.0
17 la a0, __nuclei_start
23 la a0, _start0800
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| /Zephyr-latest/tests/arch/riscv/userspace/riscv_gp/src/ |
| D | main.c | 4 * SPDX-License-Identifier: Apache-2.0
30 __asm__ volatile("la %0, __global_pointer$" : "=r" (gp_test_val)); in rogue_user_fn()
50 __asm__ volatile("la %0, __global_pointer$" : "=r" (gp_test_val)); in rogue_user_fn()
65 __asm__ volatile("la %0, __global_pointer$" : "=r" (gp_test_val)); in ZTEST_USER()
73 rogue_user_fn, NULL, NULL, NULL, -1, K_USER, K_NO_WAIT); in ZTEST_USER()
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| /Zephyr-latest/soc/qemu/malta/ |
| D | vector.S | 4 * SPDX-License-Identifier: Apache-2.0
18 la v0, __initialize
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| /Zephyr-latest/soc/espressif/esp32c2/ |
| D | soc_irq.S | 3 * SPDX-License-Identifier: Apache-2.0
14 addi sp, sp,-4
16 la t1, soc_intr_get_next_source
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| /Zephyr-latest/soc/espressif/esp32c3/ |
| D | soc_irq.S | 3 * SPDX-License-Identifier: Apache-2.0
14 addi sp, sp,-4
16 la t1, soc_intr_get_next_source
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| /Zephyr-latest/soc/espressif/esp32c6/ |
| D | soc_irq.S | 3 * SPDX-License-Identifier: Apache-2.0
20 addi sp, sp,-4
22 la t1, soc_intr_get_next_source
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| /Zephyr-latest/soc/andestech/ae350/ |
| D | start.S | 4 * SPDX-License-Identifier: Apache-2.0
21 la t0, _ITB_BASE_
33 * Enable D cache with HW prefetcher, D-cache write-around
57 /* Enable misaligned access and non-blocking load */
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| /Zephyr-latest/.github/workflows/ |
| D | codecov.yaml | 5 - cron: '25 06,18 * * *'
8 group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
9 cancel-in-progress: true
13 if: github.repository_owner == 'zephyrproject-rtos'
14 runs-on:
15 group: zephyr-runner-v2-linux-x64-4xlarge
17 image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
18 options: '--entrypoint /bin/bash'
20 fail-fast: false
24 - platform: 'mps2/an385'
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| D | coding_guidelines.yml | 7 runs-on: ubuntu-22.04
10 - name: Checkout the code
14 fetch-depth: 0
16 - name: cache-pip
20 key: ${{ runner.os }}-pip-${{ hashFiles('.github/workflows/coding_guidelines.yml') }}
22 - name: Install python dependencies
27 - name: Install Packages
29 sudo apt-get update
30 sudo apt-get install coccinelle
32 - name: Run Coding Guidelines Checks
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| D | compliance.yml | 6 - edited
7 - opened
8 - reopened
9 - synchronize
13 runs-on: ubuntu-22.04
16 - name: Update PATH for west
20 - name: Checkout the code
24 fetch-depth: 0
26 - name: Rebase onto the target branch
30 git config --global user.email "you@example.com"
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| /Zephyr-latest/samples/subsys/fs/format/ |
| D | README.rst | 1 .. zephyr:code-sample:: fs-format
3 :relevant-api: file_system_api
29 .. zephyr-app-commands::
30 :zephyr-app: samples/subsys/fs/format
35 The RAM disk sample for the MIMXRT1064-EVK board can be built as follow:
37 .. zephyr-app-commands::
38 :zephyr-app: samples/subsys/fs/format
49 .. code-block:: console
52 I: FS at flash-controller@4001e000:0x7a000 is 6 0x1000-byte blocks with 512 cycle
53 I: sizes: rd 16 ; pr 16 ; ca 64 ; la 32
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_nuclei_eclic.S | 4 * SPDX-License-Identifier: Apache-2.0
8 * @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
18 * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
34 * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
37 addi sp, sp, -16
52 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
55 la t0, _sw_isr_table
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| /Zephyr-latest/soc/openisa/rv32m1/ |
| D | soc_irq.S | 4 * SPDX-License-Identifier: Apache-2.0
22 * EVENT_UNIT->INTPTPENDCLEAR = (1U << irq_num);
33 la t0, __EVENT_INTPTPENDCLEAR
46 * Zephyr's generic RISC-V mechanism for soc-specific context.
|
| D | vector.S | 4 * SPDX-License-Identifier: Apache-2.0
17 * Interrupts work the same way for both the RI5CY and ZERO-RISCY cores
27 * Note: Per RV32I restrictions, "j SOME_HANDLER" can jump within a +/- 1MiB
29 * and ZERO-RISCY is allocated 256 KiB, and these flash banks contain the
77 la t0, ivt
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| /Zephyr-latest/samples/subsys/usb/mass/ |
| D | README.rst | 1 .. zephyr:code-sample:: usb-mass
3 :relevant-api: usbd_api usbd_msc_device _usb_device_core_api file_system_api
25 The selection between a RAM-based or a FLASH-based disk and file system
26 can be chosen passing Kconfig configuration via the -D command-line switch.
28 RAM-disk Example without any file system
31 The default configurations selects RAM-based disk without any file system.
32 This example only needs additional 96KiB RAM for the RAM-disk and is intended
35 .. zephyr-app-commands::
36 :zephyr-app: samples/subsys/usb/mass
38 :gen-args: -DEXTRA_DTC_OVERLAY_FILE="ramdisk.overlay"
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| /Zephyr-latest/soc/espressif/common/ |
| D | loader.c | 4 * SPDX-License-Identifier: Apache-2.0
26 #include <zephyr/linker/linker-defs.h>
106 uint32_t app_irom_vaddr_align = map->irom_map_addr & MMU_FLASH_MASK; in map_rom_segments()
107 uint32_t app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK; in map_rom_segments()
109 uint32_t app_drom_vaddr_align = map->drom_map_addr & MMU_FLASH_MASK; in map_rom_segments()
110 uint32_t app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK; in map_rom_segments()
112 /* Traverse segments to fix flash offset changes due to post-build processing */ in map_rom_segments()
130 /* TODO: Find better end-of-segment detection */ in map_rom_segments()
132 /* Total segment count = (segments - 1) */ in map_rom_segments()
136 ESP_EARLY_LOGI(TAG, "%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)", in map_rom_segments()
[all …]
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