Lines Matching +full:- +full:la
2 * Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
6 * SPDX-License-Identifier: Apache-2.0
45 /* Convenience macro for storing callee saved register [s0 - s11] states. */
65 la \dst, _kernel + ___kernel_t_cpus_OFFSET
110 * Generic architecture-level IRQ handling, along with callouts to
111 * SoC-specific routines.
117 * Since RISC-V does not completely prescribe IRQ handling behavior,
122 * - __soc_is_irq (optional): decide if we're handling an interrupt or an
124 * - __soc_handle_irq: handle SoC-specific details for a pending IRQ
125 * (e.g. clear a pending bit in a SoC-specific register)
127 * If CONFIG_RISCV_SOC_CONTEXT_SAVE=y, calls to SoC-level context save/restore
160 sr t0, (-__struct_arch_esf_SIZEOF + __struct_arch_esf_sp_OFFSET)(sp)
170 la gp, __global_pointer$
176 /* Clear our per-thread usermode flag */
192 /* Save caller-saved registers on current thread stack. */
193 addi sp, sp, -__struct_arch_esf_SIZEOF
240 * 0000111 = LOAD-FP
241 * 0100111 = STORE-FP
246 * 1010011 = OP-FP
248 xori t1, t0, 0b1010011 /* OP-FP */
251 xori t1, t1, 0b0100111 /* LOAD-FP / STORE-FP */
261 * CSR format: csr#[31-20] src[19-15] op[14-12] dst[11-7] SYSTEM[6-0]
304 la ra, fp_trap_exit
308 no_fp: /* increment _current->arch.exception_depth */
326 * (SOC dependent). Following the RISC-V architecture spec, the MSB
329 * SOCs (like pulpino or riscv-qemu), the MSB is never set to indicate
345 * perform a context-switch or an IRQ offload. Otherwise call z_riscv_fault
391 la ra, no_reschedule
409 /* Re-activate PMP for m-mode */
435 * When an ECALL is used for a context-switch, the current thread has
440 add t1, t1, -1
468 /* Allocate space for caller-saved registers on current thread stack */
469 addi sp, sp, -__callee_saved_t_SIZEOF
471 /* Save callee-saved registers to be passed as 3rd arg */
495 /* Increment _current_cpu->nested */
506 addi sp, sp, -16
528 /* It is safe to re-enable IRQs now */
549 addi sp, sp, -4
566 la t2, _k_syscall_table
603 1: /* Re-activate PMP for m-mode */
611 /* Increment _current_cpu->nested */
623 * In RISC-V, stack pointer needs to be 16-byte aligned
625 addi sp, sp, -16
651 * (table is 2-word wide, we should shift index accordingly)
653 la t0, _sw_isr_table
673 /* Decrement _current_cpu->nested */
675 addi t2, t2, -1
698 addi sp, sp, -16
735 /* decrement _current->arch.exception_depth */
738 add t1, t1, -1
772 /* Set our per-thread usermode flag */
786 * be re-loaded further down.
799 /* Restore caller-saved registers from thread stack */