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/Zephyr-latest/drivers/reset/
DKconfig1 # Reset Controller driver configuration options
3 # Copyright (c) 2022 Andrei-Edward Popa <andrei.popa105@yahoo.com>
4 # SPDX-License-Identifier: Apache-2.0
7 # Reset Controller options
9 menuconfig RESET config
10 bool "Reset Controller drivers"
12 Reset Controller drivers. Reset node represents a region containing
13 information about reset controller device. The typical use-case is
14 for some other node's drivers to acquire a reference to the reset
15 controller node together with some reset information.
[all …]
/Zephyr-latest/dts/bindings/power/
Dnxp,s32-mc-rgm.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP S32 Module Reset Generation (MC_RGM)
6 compatible: "nxp,s32-mc-rgm"
14 func-reset-threshold:
19 Functional Reset Escalation threshold.
20 If the value of this property is 0, the Functional reset escalation
22 resets that causes a Destructive reset, if the FRET register isn't
24 Default to maximum threshold (hardware reset value).
26 dest-reset-threshold:
31 Destructive Reset Escalation threshold.
[all …]
/Zephyr-latest/include/zephyr/devicetree/
Dreset.h3 * @brief Reset Controller Devicetree macro public API header file.
7 * Copyright (c) 2022, Andrei-Edward Popa
9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-reset-controller Devicetree Reset Controller API
27 * "resets" phandle-array property at an index
31 * reset1: reset-controller@... { ... };
33 * reset2: reset-controller@... { ... };
46 * @return the node identifier for the reset controller referenced at
56 * @return a node identifier for the reset controller at index 0
65 * resets phandle-array property by name
[all …]
/Zephyr-latest/include/zephyr/drivers/
Dreset.h2 * Copyright (c) 2022 Andrei-Edward Popa <andrei.popa105@yahoo.com>
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public Reset Controller driver APIs
16 * @brief Reset Controller Interface
17 * @defgroup reset_controller_interface Reset Controller Interface
33 /** Reset controller device configuration. */
35 /** Reset controller device. */
37 /** Reset line. */
45 * devicetree node identifier, a property specifying a Reset Controller and an index.
50 * resets = <&reset 10>;
[all …]
Dhwinfo.h10 * SPDX-License-Identifier: Apache-2.0
36 * @name Reset cause flags
42 /** Software reset */
46 /** Power-on reset (POR) */
56 /** CPU lock-up detected */
64 /** Hardware reset */
66 /** User reset */
68 /** Temperature reset */
83 * based on vendor-specific assumptions of byte order. It should express the
91 * @retval -ENOSYS if there is no implementation for the particular device.
[all …]
/Zephyr-latest/dts/bindings/reset/
Dst,stm32-rcc-rctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Reset and Clock Control (RCC) node.
6 This node is in charge of reset control for AHB (Advanced High Performance)
9 To specify the reset line in a peripheral, the standard resets property needs
19 RCC reset cells are available in
20 include/zephyr/dts-bindings/reset/stm32{soc_family}_reset.h header files.
22 compatible: "st,stm32-rcc-rctl"
24 include: [reset-controller.yaml, base.yaml]
27 "#reset-cells":
30 set-bit-to-deassert:
[all …]
Dgd,gd32-rctl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
6 charge of reset control (RCTL) and clock control (CCTL) for all SoC
7 peripherals. This binding represents the reset controller (RCTL).
9 To specify the reset line in a peripheral, the standard resets property needs
19 Predefined RCU reset cells are available in
20 include/zephyr/dts-bindings/reset/gd32{xxx}.h header files, where {xxx}
23 compatible: "gd,gd32-rctl"
25 include: [reset-controller.yaml, base.yaml]
28 "#reset-cells":
[all …]
Draspberrypi,pico-reset.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Raspberry Pi Pico Reset Controller
6 compatible: "raspberrypi,pico-reset"
8 include: [base.yaml, reset-controller.yaml]
13 reg-width:
15 description: The width of the reset registers in bytes. Default is 4 bytes.
16 active-low:
18 description: Set if reset is active low. Default is 0, which means active-high.
19 "#reset-cells":
[all …]
Dintel,socfpga-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Intel SoC FPGA Reset Controller
6 compatible: "intel,socfpga-reset"
8 include: [base.yaml, reset-controller.yaml]
13 active-low:
15 description: Add this property in dts node if the reset line is active_low, otherwise do not
17 "#reset-cells":
20 reset-cells:
21 - id
Dnxp,lpc-syscon-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: LPC SYSCON Peripheral reset controller
6 compatible: "nxp,lpc-syscon-reset"
8 include: [reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
15 - id
Daspeed,ast10x0-reset.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Aspeed AST10X0 Reset Controller
6 compatible: "aspeed,ast10x0-reset"
8 include: [base.yaml, reset-controller.yaml]
11 "#reset-cells":
14 reset-cells:
15 - id
/Zephyr-latest/samples/drivers/espi/boards/
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "microchip,mec172x-board-power";
11 pwrg-gpios = <&gpio_000_036 10 GPIO_ACTIVE_HIGH>;
13 rsm-gpios = <&gpio_040_076 12 GPIO_ACTIVE_HIGH>;
21 /* Enable Target to Controller Virtual Wires GPIO 0 - 3 */
24 reset-state = "1";
25 reset-source = "ESPI_RESET";
30 reset-state = "1";
31 reset-source = "ESPI_RESET";
36 reset-state = "1";
[all …]
Dmec172xmodular_assy6930.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "microchip,mec172x-board-power";
11 pwrg-gpios = <&gpio_000_036 10 GPIO_ACTIVE_HIGH>;
13 rsm-gpios = <&gpio_040_076 12 GPIO_ACTIVE_HIGH>;
18 /* Enable Target to Controller Virtual Wires GPIO 0 - 3 */
21 reset-state = "1";
22 reset-source = "ESPI_RESET";
27 reset-state = "1";
28 reset-source = "ESPI_RESET";
33 reset-state = "1";
[all …]
/Zephyr-latest/dts/bindings/mipi-dbi/
Dnxp,lcdic.yaml2 # SPDX-License-Identifier: Apache-2.0
5 NXP LCDIC Controller. This controller implements 8080 and SPI mode MIPI-DBI
9 include: ["mipi-dbi-controller.yaml", "pinctrl-device.yaml"]
21 nxp,swap-bytes:
27 reset-gpios:
28 type: phandle-array
30 Reset GPIO pin. The controller will set this pin to logic high to reset
31 the display. If not provided, the LCDIC module's reset pin will be used
32 to reset attached displays.
34 nxp,write-inactive-cycles:
[all …]
/Zephyr-latest/dts/bindings/test/
Dvnd,reset.yaml1 # Copyright (c) 2022 Andrei-Edward Popa
2 # SPDX-License-Identifier: Apache-2.0
4 description: Test Reset Controller
6 compatible: "vnd,reset"
8 include: [base.yaml, reset-controller.yaml]
11 reg-width:
14 "#reset-cells":
17 reset-cells:
18 - id
/Zephyr-latest/dts/bindings/bluetooth/
Drenesas,bt-hci-da1453x.yaml2 # SPDX-License-Identifier: Apache-2.0
6 controller, allowing control of the GPIO used to reset the DA1453x.
8 compatible: "renesas,bt-hci-da1453x"
13 reset-gpios:
14 type: phandle-array
16 This gpio is used to reset the DA1453x.
18 reset-assert-duration-ms:
21 Minimum duration to activate the reset-gpios pin.
24 boot-duration-ms:
28 Minimum time to wait for the DA1453x to boot following a hardware reset.
/Zephyr-latest/dts/bindings/gpio/
Dnxp,pcal64xxa-base.yaml3 # SPDX-License-Identifier: Apache-2.0
5 include: [i2c-device.yaml, gpio-controller.yaml]
8 int-gpios:
9 type: phandle-array
11 GPIO connected to the controller INT pin. This pin is active-low.
13 reset-gpios:
14 type: phandle-array
16 GPIO connected to the controller RESET pin. This pin is active-low.
18 no-auto-reset:
21 This flag disables the automatic reset, which allows the implementation
[all …]
/Zephyr-latest/dts/bindings/espi/
Dmicrochip,xec-espi-vw-routing.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "microchip,xec-espi-vw-routing"
10 child-binding:
15 vw-reg:
20 vw-girq:
26 to GIRQ24 b[5]. vw-girq = <24 5>;
28 reset-state:
31 Optional default virtual wire state on reset (0 or 1).
34 - "HW_DFLT"
35 - "0"
[all …]
/Zephyr-latest/drivers/watchdog/
DKconfig.smartbond4 # SPDX-License-Identifier: Apache-2.0
15 bool "NMI pre-reset interrupt enable"
21 reset at <= -16. Timer can be frozen/resumed using
25 reset at value 0 and can not be frozen by Software.
27 only be reset with a WDOG (SYS) reset or SW reset.
/Zephyr-latest/soc/nxp/s32/common/
Dmc_rgm.c4 * SPDX-License-Identifier: Apache-2.0
16 /* Functional / External Reset Status Register */
20 /* Functional Event Reset Disable Register */
22 /* Functional Bidirectional Reset Enable Register */
24 /* Functional Reset Escalation Counter Register */
28 /* Functional Reset Escalation Threshold Register */
32 /* Destructive Reset Escalation Threshold Register */
36 /* External Reset Control Register */
40 /* Reset During Standby Status Register */
46 /* Functional Reset Entry Timeout Control Register */
[all …]
/Zephyr-latest/scripts/west_commands/runners/
Dminichlink.py3 # SPDX-License-Identifier: Apache-2.0
20 reset: bool,
28 self.reset = reset
37 def capabilities(cls) -> RunnerCaps:
38 return RunnerCaps(commands={"flash"}, flash_addr=True, erase=True, reset=True)
43 "--minichlink", default="minichlink", help="path to the minichlink binary"
46 "--terminal",
49 help="open the terminal after flashing. Implies --reset.",
51 parser.set_defaults(reset=True)
59 reset=args.reset,
[all …]
/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-qspi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
9 mx25r6435f: qspi-nor-flash@90000000 {
10 compatible = "st,stm32-qspi-nor";
12 qspi-max-frequency = <80000000>;
13 reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
14 reset-gpios-duration = <1>;
15 spi-bus-width = <4>;
19 compatible: "st,stm32-qspi-nor"
21 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
23 on-bus: qspi
[all …]
/Zephyr-latest/dts/bindings/watchdog/
Dnxp,s32-swt.yaml1 # Copyright 2022-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,s32-swt"
20 master-access-mask:
26 are chip-specific.
27 Defaults to access enabled for all masters (hardware reset value).
29 reset-on-invalid-access:
32 Set this flag to generate a reset on respond to an invalid access.
34 service-mode:
38 - "fixed"
[all …]
/Zephyr-latest/boards/st/stm32h573i_dk/support/
Dopenocd.cfg1 source [find interface/stlink-dap.cfg]
8 set BOARDNAME STM32H573I-DK
10 # Reset configuration
11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt
/Zephyr-latest/boards/st/nucleo_h503rb/support/
Dopenocd.cfg1 source [find interface/stlink-dap.cfg]
8 set BOARDNAME NUCLEO-STM32H503RB
10 # Reset configuration
11 # use hardware reset, connect under reset
18 # to reset halt just after openocd init.
22 reset halt

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