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/Zephyr-latest/include/zephyr/toolchain/
Dxcc.h52 #define __INT8_C(x) x argument
56 #define INT8_C(x) __INT8_C(x) argument
60 #define __UINT8_C(x) x ## U argument
64 #define UINT8_C(x) __UINT8_C(x) argument
68 #define __INT16_C(x) x argument
72 #define INT16_C(x) __INT16_C(x) argument
76 #define __UINT16_C(x) x ## U argument
80 #define UINT16_C(x) __UINT16_C(x) argument
84 #define __INT32_C(x) x argument
88 #define INT32_C(x) __INT32_C(x) argument
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Dllvm.h65 #define __INT64_C(x) int_c(x, __int_least64_c_suffix__) argument
66 #define __UINT64_C(x) uint_c(x, __int_least64_c_suffix__) argument
68 #define __INT64_C(x) x argument
69 #define __UINT64_C(x) x ## U argument
86 #define __INT32_C(x) int_c(x, __int_least32_c_suffix__) argument
87 #define __UINT32_C(x) uint_c(x, __int_least32_c_suffix__) argument
89 #define __INT32_C(x) x argument
90 #define __UINT32_C(x) x ## U argument
107 #define __INT16_C(x) int_c(x, __int_least16_c_suffix__) argument
108 #define __UINT16_C(x) uint_c(x, __int_least16_c_suffix__) argument
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/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dprci.h25 #define ROSC_DIV(x) (((x) & 0x2F) << 0) argument
26 #define ROSC_TRIM(x) (((x) & 0x1F) << 16) argument
27 #define ROSC_EN(x) (((x) & 0x1) << 30) argument
28 #define ROSC_RDY(x) (((x) & 0x1) << 31) argument
30 #define XOSC_EN(x) (((x) & 0x1) << 30) argument
31 #define XOSC_RDY(x) (((x) & 0x1) << 31) argument
33 #define PLL_R(x) (((x) & 0x7) << 0) argument
35 #define PLL_F(x) (((x) & 0x3F) << 4) argument
36 #define PLL_Q(x) (((x) & 0x3) << 10) argument
37 #define PLL_SEL(x) (((x) & 0x1) << 16) argument
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/Zephyr-latest/drivers/flash/
Dflash_cadence_qspi_nor_ll.h24 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
31 #define CAD_QSPI_CFG_BAUDDIV(x) FIELD_PREP(0x780000, x) argument
33 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
41 #define CAD_QSPI_DELAY_CSSOT(x) (FIELD_GET(0xff, (x)) << 0) argument
42 #define CAD_QSPI_DELAY_CSEOT(x) (FIELD_GET(0xff, (x)) << 8) argument
43 #define CAD_QSPI_DELAY_CSDADS(x) (FIELD_GET(0xff, (x)) << 16) argument
44 #define CAD_QSPI_DELAY_CSDA(x) (FIELD_GET(0xff, (x)) << 24) argument
47 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x) ((x) << 0) argument
48 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x) ((x) << 4) argument
49 #define CAD_QSPI_DEVSZ_BYTES_PER_BLOCK(x) ((x) << 16) argument
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Dflash_cadence_nand_ll.h18 #define CNF_GET_INIT_COMP(x) (FIELD_GET(BIT(9), x)) argument
19 #define CNF_GET_INIT_FAIL(x) (FIELD_GET(BIT(10), x)) argument
20 #define CNF_GET_CTRL_BUSY(x) (FIELD_GET(BIT(8), x)) argument
21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x)) argument
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x)) argument
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x)) argument
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x)) argument
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x)) argument
28 #define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x)) argument
29 #define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x)) argument
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/Zephyr-latest/drivers/sensor/ti/tmp108/
Dtmp108.h47 #define TI_TMP108_MODE_SHUTDOWN(x) 0 argument
48 #define TI_TMP108_MODE_ONE_SHOT(x) (TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_SLEEP(x)) argument
49 #define TI_TMP108_MODE_CONTINUOUS(x) TI_TMP108_CONF_M1(x) argument
50 #define TI_TMP108_MODE_MASK(x) ~(TI_TMP108_CONF_M0(x) | \ argument
54 #define TI_TMP108_FREQ_4_SECS(x) 0 argument
55 #define TI_TMP108_FREQ_1_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR0) argument
56 #define TI_TMP108_FREQ_4_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR1) argument
57 #define TI_TMP108_FREQ_16_HZ(x) (TI_TMP108_GET_CONF(x, CONF_CR1) | \ argument
59 #define TI_TMP108_FREQ_MASK(x) ~(TI_TMP108_GET_CONF(x, CONF_CR1) | \ argument
62 #define TI_TMP108_CONF_POL_LOW(x) 0 argument
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/Zephyr-latest/drivers/sensor/ti/fdc2x1x/
Dfdc2x1x.h61 #define FDC2X1X_REG_READ(x) (((x & 0xFF) << 1) | FDC2X1X_READ) argument
62 #define FDC2X1X_REG_WRITE(x) ((x & 0xFF) << 1) argument
63 #define FDC2X1X_TO_I2C_REG(x) ((x) >> 1) argument
67 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_SET(x) (((x) & 0x3) << 12) argument
68 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_GET(x) (((x) >> 12) & 0x3) argument
70 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_SET(x) ((x) & 0x1FF) argument
71 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_GET(x) (((x) >> 0) & 0x1FF) argument
74 #define FDC2X1X_STATUS_ERR_CHAN(x) (((x) >> 14) & 0x3) argument
75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1) argument
76 #define FDC2X1X_STATUS_ERR_AHW(x) (((x) >> 10) & 0x1) argument
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/Zephyr-latest/include/zephyr/dt-bindings/pwm/
Dpwm.h24 #define PWM_NSEC(x) (x) argument
26 #define PWM_USEC(x) (PWM_NSEC(x) * 1000UL) argument
28 #define PWM_MSEC(x) (PWM_USEC(x) * 1000UL) argument
30 #define PWM_SEC(x) (PWM_MSEC(x) * 1000UL) argument
32 #define PWM_HZ(x) (PWM_SEC(1UL) / (x)) argument
34 #define PWM_KHZ(x) (PWM_HZ((x) * 1000UL)) argument
/Zephyr-latest/soc/nxp/lpc/lpc11u6x/
Dsoc.h40 #define IOCON_PIO_FUNC(x) (((x) & 0x7)) argument
42 #define IOCON_PIO_MODE(x) (((x) & 0x3) << 3) argument
44 #define IOCON_PIO_HYS(x) (((x) & 0x1) << 5) argument
46 #define IOCON_PIO_INVERT(x) (((x) & 0x1) << 2) argument
48 #define IOCON_PIO_OD(x) (((x) & 0x1) << 10) argument
50 #define IOCON_PIO_SMODE(x) (((x) & 0x3) << 11) argument
52 #define IOCON_PIO_CLKDIV(x) (((x) & 0x7) << 13) argument
72 #define IOCON_PIO_ADMODE(x) (((x) & 0x1) << 7) argument
74 #define IOCON_PIO_FILTER(x) (((x) & 0x1) << 8) argument
91 #define IOCON_PIO_I2CMODE(x) (((x) & 0x3) << 8) argument
/Zephyr-latest/samples/subsys/portability/cmsis_rtos_v1/philosophers/src/
Dphil_obj_abstract.h41 #define fork_init(x) osSemaphoreCreate(osSemaphore(##x), 1) argument
42 #define take(x) osSemaphoreWait(x, osWaitForever) argument
43 #define drop(x) osSemaphoreRelease(x) argument
55 #define fork_init(x) osMutexCreate(osMutex(##x)); argument
56 #define take(x) osMutexWait(x, 0) argument
57 #define drop(x) osMutexRelease(x) argument
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v1.h30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
31 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
40 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
46 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
58 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
60 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
100 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
101 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
103 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
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Dssp_regs_v2.h31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
32 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
41 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
47 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
59 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) argument
61 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) argument
101 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
102 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
104 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
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Dssp_regs_v3.h32 #define PCMSyCM_OFFSET(x) 0x16 + 0x4*(x) argument
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) argument
39 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) argument
48 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) argument
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) argument
54 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) argument
96 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) argument
97 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) argument
98 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) argument
99 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x) argument
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/Zephyr-latest/samples/subsys/portability/cmsis_rtos_v2/philosophers/src/
Dphil_obj_abstract.h45 #define fork_init(x) osSemaphoreNew(1, 1, &sema_attr[x]) argument
46 #define take(x) osSemaphoreAcquire(x, osWaitForever) argument
47 #define drop(x) osSemaphoreRelease(x) argument
61 #define fork_init(x) osMutexNew(&mutex_attr[x]) argument
62 #define take(x) osMutexAcquire(x, osWaitForever) argument
63 #define drop(x) osMutexRelease(x) argument
/Zephyr-latest/samples/philosophers/src/
Dphil_obj_abstract.h53 #define fork_init(x) k_sem_init(x, 1, 1) argument
55 #define take(x) k_sem_take(x, K_FOREVER) argument
56 #define drop(x) k_sem_give(x) argument
69 #define fork_init(x) k_mutex_init(x) argument
71 #define take(x) k_mutex_lock(x, K_FOREVER) argument
72 #define drop(x) k_mutex_unlock(x) argument
83 #define fork_init(x) do { \ argument
88 #define take(x) do { \ argument
92 #define drop(x) k_stack_push(x, MAGIC) argument
103 #define fork_init(x) do { \ argument
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/Zephyr-latest/include/zephyr/xen/
Dgeneric.h14 #define XEN_PFN_UP(x) (unsigned long)(((x) + XEN_PAGE_SIZE-1) >> XEN_PAGE_SHIFT) argument
15 #define XEN_PFN_DOWN(x) (unsigned long)((x) >> XEN_PAGE_SHIFT) argument
16 #define XEN_PFN_PHYS(x) ((unsigned long)(x) << XEN_PAGE_SHIFT) argument
17 #define XEN_PHYS_PFN(x) (unsigned long)((x) >> XEN_PAGE_SHIFT) argument
19 #define xen_to_phys(x) ((unsigned long) (x)) argument
20 #define xen_to_virt(x) ((void *) (x)) argument
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dprci.h27 #define PLL_R(x) (((x) & 0x3f) << 0) argument
28 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
29 #define PLL_Q(x) (((x) & 0x7) << 15) argument
30 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
31 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
32 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
33 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
40 #define CORECLKSEL_CORECLKSEL(x) (((x) & 0x1) << 0) argument
/Zephyr-latest/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/
Dchip_chipregs.h15 #define ECREG(x) (*((volatile unsigned char *)fake_ecreg((intptr_t)x))) argument
16 #define ECREG_u16(x) (*((volatile unsigned short *)fake_ecreg((intptr_t)x))) argument
17 #define ECREG_u32(x) (*((volatile unsigned long *)fake_ecreg((intptr_t)x))) argument
/Zephyr-latest/include/zephyr/toolchain/iar/
Diccarm.h152 #define __aligned(x) __attribute__((__aligned__(x))) argument
160 #define __alignof(x) alignof(x) argument
162 #define __alignof(x) _Alignof(x) argument
205 #define ARG_UNUSED(x) (void)(x) argument
207 #define likely(x) (__builtin_expect((bool)!!(x), true) != 0L) argument
208 #define unlikely(x) (__builtin_expect((bool)!!(x), false) != 0L) argument
209 #define POPCOUNT(x) __builtin_popcount(x) argument
366 #define Z_POW2_CEIL(x) \ argument
375 #define Z_IS_POW2(x) (((x) != 0) && (((x) & ((x)-1)) == 0)) argument
378 #define __INT8_C(x) x argument
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/Zephyr-latest/lib/libc/minimal/include/
Dstdint.h127 #define __INT8_C(x) x argument
131 #define INT8_C(x) __INT8_C(x) argument
135 #define __UINT8_C(x) x ## U argument
139 #define UINT8_C(x) __UINT8_C(x) argument
143 #define __INT16_C(x) x argument
147 #define INT16_C(x) __INT16_C(x) argument
151 #define __UINT16_C(x) x ## U argument
155 #define UINT16_C(x) __UINT16_C(x) argument
159 #define __INT32_C(x) x argument
163 #define INT32_C(x) __INT32_C(x) argument
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/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dsoc.h16 #define DSP_WCT_IRQ(x) \ argument
19 #define DSP_WCT_CS_TA(x) BIT(x) argument
20 #define DSP_WCT_CS_TT(x) BIT(4 + x) argument
/Zephyr-latest/dts/common/
Dmem.h10 #define DT_SIZE_K(x) ((x) * 1024) argument
11 #define DT_SIZE_M(x) (DT_SIZE_K(x) * 1024) argument
14 #define _DT_DO_CONCAT(x, y) x ## y argument
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/openisa/hal/RV32M1/
Dticker.h33 #define HAL_TICKER_US_TO_TICKS(x) \ argument
43 #define HAL_TICKER_US_TO_TICKS_CEIL(x) \ argument
51 #define HAL_TICKER_TICKS_TO_US(x) \ argument
58 #define HAL_TICKER_REMAINDER(x) \ argument
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dprci.h33 #define PLL_R(x) (((x) & 0x3f) << 0) argument
34 #define PLL_F(x) (((x) & 0x1ff) << 6) argument
35 #define PLL_Q(x) (((x) & 0x7) << 15) argument
36 #define PLL_RANGE(x) (((x) & 0x7) << 18) argument
37 #define PLL_BYPASS(x) (((x) & 0x1) << 24) argument
38 #define PLL_FSE(x) (((x) & 0x1) << 25) argument
39 #define PLL_LOCK(x) (((x) & 0x1) << 31) argument
53 #define OUTDIV_PLLCKE(x) (((x) & 0x1) << 31) argument
58 #define CLKSEL_SEL(x) (((x) & 0x1) << 0) argument
71 #define COREPLLSEL_SEL(x) (((x) & 0x1) << 0) argument
/Zephyr-latest/drivers/sensor/adi/adxl372/
Dadxl372.h97 #define ADXL372_REG_READ(x) (((x & 0xFF) << 1) | ADXL372_READ) argument
98 #define ADXL372_REG_WRITE(x) ((x & 0xFF) << 1) argument
99 #define ADXL372_TO_I2C_REG(x) ((x) >> 1) argument
103 #define ADXL372_POWER_CTL_INSTANT_ON_TH_MODE(x) (((x) & 0x1) << 5) argument
105 #define ADXL372_POWER_CTL_FIL_SETTLE_MODE(x) (((x) & 0x1) << 4) argument
107 #define ADXL372_POWER_CTL_LPF_DIS_MODE(x) (((x) & 0x1) << 3) argument
109 #define ADXL372_POWER_CTL_HPF_DIS_MODE(x) (((x) & 0x1) << 2) argument
111 #define ADXL372_POWER_CTL_MODE(x) (((x) & 0x3) << 0) argument
115 #define ADXL372_MEASURE_AUTOSLEEP_MODE(x) (((x) & 0x1) << 6) argument
117 #define ADXL372_MEASURE_LINKLOOP_MODE(x) (((x) & 0x3) << 4) argument
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