Home
last modified time | relevance | path

Searched defs:vaddr (Results 1 – 25 of 25) sorted by relevance

/hal_espressif-latest/components/soc/esp32/include/soc/
Dext_mem_defs.h33 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
35 #define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr) argument
36 #define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr) argument
37 #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) argument
38 #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dext_mem_defs.h46 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
48 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
49 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
50 #define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr) argument
51 #define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr) argument
52 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
53 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
54 #define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr) argument
55 #define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr) argument
56 #define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dext_mem_defs.h31 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
33 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
35 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
36 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dext_mem_defs.h31 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
33 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
35 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
36 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dext_mem_defs.h29 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
31 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
32 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
33 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
34 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dext_mem_defs.h39 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
41 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
42 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
43 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
44 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dext_mem_defs.h28 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name… argument
30 #define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) argument
31 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) argument
32 #define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) argument
33 #define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) argument
/hal_espressif-latest/components/hal/
Dmmu_hal.c75 void mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uin… in mmu_hal_map_region()
99 void mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len) in mmu_hal_unmap_region()
115 bool mmu_hal_vaddr_to_paddr(uint32_t mmu_id, uint32_t vaddr, uint32_t *out_paddr, mmu_target_t *out… in mmu_hal_vaddr_to_paddr()
Dcache_hal.c168 void cache_hal_invalidate_addr(uint32_t vaddr, uint32_t size) in cache_hal_invalidate_addr()
176 void cache_hal_writeback_addr(uint32_t vaddr, uint32_t size) in cache_hal_writeback_addr()
/hal_espressif-latest/components/esp_hw_support/port/esp32/
Dcache_sram_mmu.c56 unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int pad… in cache_sram_mmu_set()
132 unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int ps… in cache_sram_mmu_set()
/hal_espressif-latest/components/esp_system/port/arch/xtensa/
Dpanic_arch.c174 uint32_t vaddr = 0, size = 0; in print_cache_err_details() local
297 uint32_t vaddr = 0, size = 0; in print_cache_err_details() local
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
139 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
139 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
139 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32/include/hal/
Dmmu_ll.h31 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
144 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
138 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/esp_mm/
Desp_cache.c66 uint32_t vaddr = (uint32_t)addr; in esp_cache_msync() local
Desp_mmu_map.c318 uint32_t vaddr = 0; in esp_mmu_map_reserve_block_with_caps() local
702 static bool NOINLINE_ATTR IRAM_ATTR s_vaddr_to_paddr(uint32_t vaddr, esp_paddr_t *out_paddr, mmu_ta… in s_vaddr_to_paddr()
713 esp_err_t esp_mmu_vaddr_to_paddr(void *vaddr, esp_paddr_t *out_paddr, mmu_target_t *out_target) in esp_mmu_vaddr_to_paddr()
746 uint32_t vaddr = 0; in esp_mmu_paddr_to_vaddr() local
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dmmu_ll.h29 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
137 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dmmu_ll.h30 static inline uint32_t mmu_ll_vaddr_to_laddr(uint32_t vaddr) in mmu_ll_vaddr_to_laddr()
141 static inline uint32_t mmu_ll_get_entry_id(uint32_t mmu_id, uint32_t vaddr) in mmu_ll_get_entry_id()
/hal_espressif-latest/components/spi_flash/
Dflash_mmap.c321 uint32_t vaddr = 0; in is_page_mapped_in_cache() local
347 const void *vaddr = NULL; in spi_flash_check_and_flush_cache() local
/hal_espressif-latest/components/esp_rom/include/esp32/rom/
Dcache.h68 …)) unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned in… in cache_flash_mmu_set()
/hal_espressif-latest/components/xtensa/include/xtensa/
Dhal.h1172 #define XTHAL_MPU_ENTRY(vaddr, valid, access, memtype) \ argument
1181 #define XTHAL_MPU_ENTRY_SET_VSTARTADDR(x, vaddr) (x).as = \ argument
/hal_espressif-latest/components/esp_rom/include/esp32c6/rom/
Dcache.h604 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ argument
/hal_espressif-latest/components/esp_rom/include/esp32h2/rom/
Dcache.h607 #define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \ argument