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Searched defs:CTRL (Results 1 – 25 of 37) sorted by relevance

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/hal_microchip-latest/mec/mec1501/component/
Dtimer.h173 __IOM uint32_t CTRL; /*!< (@ 0x00000010) BTMR Control */ member
236 __IOM uint16_t CTRL; /*!< (@ 0x00000004) HTMR Control */ member
315 __IOM uint32_t CTRL; /*!< (@ 0x00000000) CCT Control */ member
379 __IOM uint8_t CTRL; /*!< (@ 0x00000008) RTMR Control */ member
477 __IOM uint32_t CTRL; /*! (@ 0x00000000) WKTMR control */ member
Dtfdp.h85 __IOM uint32_t CTRL; /*!< (@ 0x0004) Control register */ member
Dps2_ctrl.h161 __IOM uint32_t CTRL; /*!< (@ 0x0004) PS/2 Control */ member
Dwdt.h135 __IOM uint16_t CTRL; /*!< (@ 0x00000004) WDT Control */ member
Ddma.h491 __IOM uint32_t CTRL; /*!< (@ 0x00000010) DMA channel control */ member
516 __IOM uint32_t CTRL; /*!< (@ 0x00000010) DMA channel control */ member
/hal_microchip-latest/mec5/devices/common/
Dmec5_htmr_v1.h19 …__IOM uint32_t CTRL; /*!< (@ 0x00000004) Hibernation timer control … member
Dmec5_rtmr_v1.h20 …__IOM uint32_t CTRL; /*!< (@ 0x00000008) RTOS timer control … member
Dmec5_tfdp_v1.h20 …__IOM uint8_t CTRL; /*!< (@ 0x00000004) TFDP control … member
Dmec5_rcid_v1.h18 …__IOM uint32_t CTRL; /*!< (@ 0x00000000) RC ID control … member
Dmec5_wdt_v2.h19 …__IOM uint32_t CTRL; /*!< (@ 0x00000004) WDT Control … member
Dmec5_btmr_v1.h22 …__IOM uint32_t CTRL; /*!< (@ 0x00000010) Basic timer control … member
Dmec5_tach_v1.h18 …__IOM uint32_t CTRL; /*!< (@ 0x00000000) Tachometer control … member
Dmec5_ps2_v1.h20 …__IOM uint8_t CTRL; /*!< (@ 0x00000004) PS2 control … member
Dmec5_gspi_v1.h19 …__IOM uint32_t CTRL; /*!< (@ 0x00000004) GSPI control … member
Dmec5_ctmr_v1.h18 …__IOM uint32_t CTRL; /*!< (@ 0x00000000) 16-bit Event Counter/Timer Contr… member
Dmec5_wktmr_bgpo_v1.h18 …__IOM uint32_t CTRL; /*!< (@ 0x00000000) Week timer control … member
Dmec5_gpio_8f_6port_v1_5.h18 …__IOM uint32_t CTRL[192]; /*!< (@ 0x00000000) GPIO Control n … member
Dmec5_rtc_v1.h33 …__IOM uint8_t CTRL; /*!< (@ 0x00000010) RTC control … member
Dmec5_peci_v1.h22 …__IOM uint8_t CTRL; /*!< (@ 0x00000008) PECI control … member
Dmec5_dmac_ch16_v2.h21 …__IOM uint32_t CTRL; /*!< (@ 0x00000010) Channel n Control … member
Dmec5_dmac_ch20_v2.h21 …__IOM uint32_t CTRL; /*!< (@ 0x00000010) Channel n Control … member
/hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/
Dccl_component_fixup_pic32cxsg.h61 __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ member
Dcmcc_component_fixup_pic32cxsg.h146 …__O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Regist… member
Dport_component_fixup_pic32cxsg.h189 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ member
/hal_microchip-latest/mpfs/drivers/mss/mss_i2c/
Dmss_i2c.h524 volatile uint8_t CTRL; member

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