1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_WKTMR_BGPO_V1_H 7 #define _MEC5_WKTMR_BGPO_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief Week timer (MEC_WKTMR) 15 */ 16 17 typedef struct mec_wktmr_regs { /*!< (@ 0x4000AC80) MEC_WKTMR Structure */ 18 __IOM uint32_t CTRL; /*!< (@ 0x00000000) Week timer control */ 19 __IOM uint32_t COUNT; /*!< (@ 0x00000004) Week timer alarm counter */ 20 __IOM uint32_t COMP; /*!< (@ 0x00000008) Week timer compare */ 21 __IOM uint32_t CLKDIV; /*!< (@ 0x0000000C) Week timer clock divider */ 22 __IOM uint32_t SSIS; /*!< (@ 0x00000010) Week timer sub-second interrupt select */ 23 __IOM uint32_t SWCR; /*!< (@ 0x00000014) Week timer sub-week control */ 24 __IOM uint32_t SWAC; /*!< (@ 0x00000018) Week timer sub-week alarm counter */ 25 __IOM uint32_t BGPO_DATA; /*!< (@ 0x0000001C) Week timer BGPO data */ 26 __IOM uint32_t BGPO_PWR; /*!< (@ 0x00000020) Week timer BGPO power select */ 27 __IOM uint32_t BGPO_RESET; /*!< (@ 0x00000024) Week timer BGPO select reset event */ 28 } MEC_WKTMR_Type; /*!< Size = 40 (0x28) */ 29 30 /** @} */ /* End of group Device_Peripheral_peripherals */ 31 32 /** @addtogroup PosMask_peripherals 33 * @{ 34 */ 35 /* ========================================================= CTRL ========================================================== */ 36 #define MEC_WKTMR_CTRL_TIMER_Pos (0UL) /*!< TIMER (Bit 0) */ 37 #define MEC_WKTMR_CTRL_TIMER_Msk (0x1UL) /*!< TIMER (Bitfield-Mask: 0x01) */ 38 #define MEC_WKTMR_CTRL_PUPEV_Pos (6UL) /*!< PUPEV (Bit 6) */ 39 #define MEC_WKTMR_CTRL_PUPEV_Msk (0x40UL) /*!< PUPEV (Bitfield-Mask: 0x01) */ 40 /* ========================================================= SSIS ========================================================== */ 41 #define MEC_WKTMR_SSIS_SPISR_Pos (0UL) /*!< SPISR (Bit 0) */ 42 #define MEC_WKTMR_SSIS_SPISR_Msk (0xfUL) /*!< SPISR (Bitfield-Mask: 0x0f) */ 43 /* ========================================================= SWCR ========================================================== */ 44 #define MEC_WKTMR_SWCR_SUB_PUPEV_Pos (0UL) /*!< SUB_PUPEV (Bit 0) */ 45 #define MEC_WKTMR_SWCR_SUB_PUPEV_Msk (0x1UL) /*!< SUB_PUPEV (Bitfield-Mask: 0x01) */ 46 #define MEC_WKTMR_SWCR_PUPEV_Pos (1UL) /*!< PUPEV (Bit 1) */ 47 #define MEC_WKTMR_SWCR_PUPEV_Msk (0x2UL) /*!< PUPEV (Bitfield-Mask: 0x01) */ 48 #define MEC_WKTMR_SWCR_SYSPWR_PRES_Pos (5UL) /*!< SYSPWR_PRES (Bit 5) */ 49 #define MEC_WKTMR_SWCR_SYSPWR_PRES_Msk (0x20UL) /*!< SYSPWR_PRES (Bitfield-Mask: 0x01) */ 50 #define MEC_WKTMR_SWCR_AUTO_RELOAD_Pos (6UL) /*!< AUTO_RELOAD (Bit 6) */ 51 #define MEC_WKTMR_SWCR_AUTO_RELOAD_Msk (0x40UL) /*!< AUTO_RELOAD (Bitfield-Mask: 0x01) */ 52 #define MEC_WKTMR_SWCR_SUBSRC_Pos (7UL) /*!< SUBSRC (Bit 7) */ 53 #define MEC_WKTMR_SWCR_SUBSRC_Msk (0x380UL) /*!< SUBSRC (Bitfield-Mask: 0x07) */ 54 /* ========================================================= SWAC ========================================================== */ 55 #define MEC_WKTMR_SWAC_SUB_LOAD_Pos (0UL) /*!< SUB_LOAD (Bit 0) */ 56 #define MEC_WKTMR_SWAC_SUB_LOAD_Msk (0x1ffUL) /*!< SUB_LOAD (Bitfield-Mask: 0x1ff) */ 57 #define MEC_WKTMR_SWAC_SUB_CNT_Pos (16UL) /*!< SUB_CNT (Bit 16) */ 58 #define MEC_WKTMR_SWAC_SUB_CNT_Msk (0x1ff0000UL) /*!< SUB_CNT (Bitfield-Mask: 0x1ff) */ 59 /* ======================================================= BGPO_DATA ======================================================= */ 60 #define MEC_WKTMR_BGPO_DATA_BGPO_0_Pos (0UL) /*!< BGPO_0 (Bit 0) */ 61 #define MEC_WKTMR_BGPO_DATA_BGPO_0_Msk (0x1UL) /*!< BGPO_0 (Bitfield-Mask: 0x01) */ 62 #define MEC_WKTMR_BGPO_DATA_BGPO_1_Pos (1UL) /*!< BGPO_1 (Bit 1) */ 63 #define MEC_WKTMR_BGPO_DATA_BGPO_1_Msk (0x2UL) /*!< BGPO_1 (Bitfield-Mask: 0x01) */ 64 #define MEC_WKTMR_BGPO_DATA_BGPO_2_Pos (2UL) /*!< BGPO_2 (Bit 2) */ 65 #define MEC_WKTMR_BGPO_DATA_BGPO_2_Msk (0x4UL) /*!< BGPO_2 (Bitfield-Mask: 0x01) */ 66 #define MEC_WKTMR_BGPO_DATA_BGPO_3_Pos (3UL) /*!< BGPO_3 (Bit 3) */ 67 #define MEC_WKTMR_BGPO_DATA_BGPO_3_Msk (0x8UL) /*!< BGPO_3 (Bitfield-Mask: 0x01) */ 68 #define MEC_WKTMR_BGPO_DATA_BGPO_4_Pos (4UL) /*!< BGPO_4 (Bit 4) */ 69 #define MEC_WKTMR_BGPO_DATA_BGPO_4_Msk (0x10UL) /*!< BGPO_4 (Bitfield-Mask: 0x01) */ 70 #define MEC_WKTMR_BGPO_DATA_BGPO_5_Pos (5UL) /*!< BGPO_5 (Bit 5) */ 71 #define MEC_WKTMR_BGPO_DATA_BGPO_5_Msk (0x20UL) /*!< BGPO_5 (Bitfield-Mask: 0x01) */ 72 /* ======================================================= BGPO_PWR ======================================================== */ 73 #define MEC_WKTMR_BGPO_PWR_BGPO_0_Pos (0UL) /*!< BGPO_0 (Bit 0) */ 74 #define MEC_WKTMR_BGPO_PWR_BGPO_0_Msk (0x1UL) /*!< BGPO_0 (Bitfield-Mask: 0x01) */ 75 #define MEC_WKTMR_BGPO_PWR_BGPO_1_Pos (1UL) /*!< BGPO_1 (Bit 1) */ 76 #define MEC_WKTMR_BGPO_PWR_BGPO_1_Msk (0x2UL) /*!< BGPO_1 (Bitfield-Mask: 0x01) */ 77 #define MEC_WKTMR_BGPO_PWR_BGPO_2_Pos (2UL) /*!< BGPO_2 (Bit 2) */ 78 #define MEC_WKTMR_BGPO_PWR_BGPO_2_Msk (0x4UL) /*!< BGPO_2 (Bitfield-Mask: 0x01) */ 79 #define MEC_WKTMR_BGPO_PWR_BGPO_3_Pos (3UL) /*!< BGPO_3 (Bit 3) */ 80 #define MEC_WKTMR_BGPO_PWR_BGPO_3_Msk (0x8UL) /*!< BGPO_3 (Bitfield-Mask: 0x01) */ 81 #define MEC_WKTMR_BGPO_PWR_BGPO_4_Pos (4UL) /*!< BGPO_4 (Bit 4) */ 82 #define MEC_WKTMR_BGPO_PWR_BGPO_4_Msk (0x10UL) /*!< BGPO_4 (Bitfield-Mask: 0x01) */ 83 #define MEC_WKTMR_BGPO_PWR_BGPO_5_Pos (5UL) /*!< BGPO_5 (Bit 5) */ 84 #define MEC_WKTMR_BGPO_PWR_BGPO_5_Msk (0x20UL) /*!< BGPO_5 (Bitfield-Mask: 0x01) */ 85 /* ====================================================== BGPO_RESET ======================================================= */ 86 #define MEC_WKTMR_BGPO_RESET_BGPO_0_Pos (0UL) /*!< BGPO_0 (Bit 0) */ 87 #define MEC_WKTMR_BGPO_RESET_BGPO_0_Msk (0x1UL) /*!< BGPO_0 (Bitfield-Mask: 0x01) */ 88 #define MEC_WKTMR_BGPO_RESET_BGPO_1_Pos (1UL) /*!< BGPO_1 (Bit 1) */ 89 #define MEC_WKTMR_BGPO_RESET_BGPO_1_Msk (0x2UL) /*!< BGPO_1 (Bitfield-Mask: 0x01) */ 90 #define MEC_WKTMR_BGPO_RESET_BGPO_2_Pos (2UL) /*!< BGPO_2 (Bit 2) */ 91 #define MEC_WKTMR_BGPO_RESET_BGPO_2_Msk (0x4UL) /*!< BGPO_2 (Bitfield-Mask: 0x01) */ 92 #define MEC_WKTMR_BGPO_RESET_BGPO_3_Pos (3UL) /*!< BGPO_3 (Bit 3) */ 93 #define MEC_WKTMR_BGPO_RESET_BGPO_3_Msk (0x8UL) /*!< BGPO_3 (Bitfield-Mask: 0x01) */ 94 #define MEC_WKTMR_BGPO_RESET_BGPO_4_Pos (4UL) /*!< BGPO_4 (Bit 4) */ 95 #define MEC_WKTMR_BGPO_RESET_BGPO_4_Msk (0x10UL) /*!< BGPO_4 (Bitfield-Mask: 0x01) */ 96 #define MEC_WKTMR_BGPO_RESET_BGPO_5_Pos (5UL) /*!< BGPO_5 (Bit 5) */ 97 #define MEC_WKTMR_BGPO_RESET_BGPO_5_Msk (0x20UL) /*!< BGPO_5 (Bitfield-Mask: 0x01) */ 98 99 /** @} */ /* End of group PosMask_peripherals */ 100 101 /** @addtogroup EnumValue_peripherals 102 * @{ 103 */ 104 /* ========================================================= CTRL ========================================================== */ 105 /* ============================================= MEC_WKTMR CTRL TIMER [0..0] ============================================== */ 106 typedef enum { /*!< MEC_WKTMR_CTRL_TIMER */ 107 MEC_WKTMR_CTRL_TIMER_EN = 1, /*!< EN : Enable */ 108 } MEC_WKTMR_CTRL_TIMER_Enum; 109 110 /* ============================================= MEC_WKTMR CTRL PUPEV [6..6] ============================================== */ 111 typedef enum { /*!< MEC_WKTMR_CTRL_PUPEV */ 112 MEC_WKTMR_CTRL_PUPEV_EN = 1, /*!< EN : Enable */ 113 } MEC_WKTMR_CTRL_PUPEV_Enum; 114 115 /* ========================================================= COUNT ========================================================= */ 116 /* ========================================================= COMP ========================================================== */ 117 /* ======================================================== CLKDIV ========================================================= */ 118 /* ========================================================= SSIS ========================================================== */ 119 /* ============================================= MEC_WKTMR SSIS SPISR [0..3] ============================================== */ 120 typedef enum { /*!< MEC_WKTMR_SSIS_SPISR */ 121 MEC_WKTMR_SSIS_SPISR_DIS = 0, /*!< DIS : Subsecond interrupt events disabled */ 122 MEC_WKTMR_SSIS_SPISR_HZ_2 = 1, /*!< HZ_2 : 2 Hz subsecond interrupt rate */ 123 MEC_WKTMR_SSIS_SPISR_HZ_4 = 2, /*!< HZ_4 : 4 Hz subsecond interrupt rate */ 124 MEC_WKTMR_SSIS_SPISR_HZ_8 = 3, /*!< HZ_8 : 8 Hz subsecond interrupt rate */ 125 MEC_WKTMR_SSIS_SPISR_HZ_16 = 4, /*!< HZ_16 : 16 Hz subsecond interrupt rate */ 126 MEC_WKTMR_SSIS_SPISR_HZ_32 = 5, /*!< HZ_32 : 32 Hz subsecond interrupt rate */ 127 MEC_WKTMR_SSIS_SPISR_HZ_64 = 6, /*!< HZ_64 : 64 Hz subsecond interrupt rate */ 128 MEC_WKTMR_SSIS_SPISR_HZ_128 = 7, /*!< HZ_128 : 128 Hz subsecond interrupt rate */ 129 MEC_WKTMR_SSIS_SPISR_HZ_256 = 8, /*!< HZ_256 : 256 Hz subsecond interrupt rate */ 130 MEC_WKTMR_SSIS_SPISR_HZ_512 = 9, /*!< HZ_512 : 512 Hz subsecond interrupt rate */ 131 MEC_WKTMR_SSIS_SPISR_KHZ_1 = 10, /*!< KHZ_1 : 1 KHz subsecond interrupt rate */ 132 MEC_WKTMR_SSIS_SPISR_KHZ_2 = 11, /*!< KHZ_2 : 2 KHz subsecond interrupt rate */ 133 MEC_WKTMR_SSIS_SPISR_KHZ_4 = 12, /*!< KHZ_4 : 4 KHz subsecond interrupt rate */ 134 MEC_WKTMR_SSIS_SPISR_KHZ_8 = 13, /*!< KHZ_8 : 8 KHz subsecond interrupt rate */ 135 MEC_WKTMR_SSIS_SPISR_KHZ_16 = 14, /*!< KHZ_16 : 16 KHz subsecond interrupt rate */ 136 MEC_WKTMR_SSIS_SPISR_KHZ_32 = 15, /*!< KHZ_32 : 32 KHz subsecond interrupt rate */ 137 } MEC_WKTMR_SSIS_SPISR_Enum; 138 139 /* ========================================================= SWCR ========================================================== */ 140 /* =========================================== MEC_WKTMR SWCR SUB_PUPEV [0..0] ============================================ */ 141 typedef enum { /*!< MEC_WKTMR_SWCR_SUB_PUPEV */ 142 MEC_WKTMR_SWCR_SUB_PUPEV_STS = 1, /*!< STS : Status Active */ 143 } MEC_WKTMR_SWCR_SUB_PUPEV_Enum; 144 145 /* ============================================= MEC_WKTMR SWCR PUPEV [1..1] ============================================== */ 146 typedef enum { /*!< MEC_WKTMR_SWCR_PUPEV */ 147 MEC_WKTMR_SWCR_PUPEV_STS = 1, /*!< STS : Status Active */ 148 } MEC_WKTMR_SWCR_PUPEV_Enum; 149 150 /* ========================================== MEC_WKTMR SWCR SYSPWR_PRES [5..5] =========================================== */ 151 typedef enum { /*!< MEC_WKTMR_SWCR_SYSPWR_PRES */ 152 MEC_WKTMR_SWCR_SYSPWR_PRES_EN = 1, /*!< EN : Enable */ 153 } MEC_WKTMR_SWCR_SYSPWR_PRES_Enum; 154 155 /* ========================================== MEC_WKTMR SWCR AUTO_RELOAD [6..6] =========================================== */ 156 typedef enum { /*!< MEC_WKTMR_SWCR_AUTO_RELOAD */ 157 MEC_WKTMR_SWCR_AUTO_RELOAD_DIS = 1, /*!< DIS : Disable */ 158 } MEC_WKTMR_SWCR_AUTO_RELOAD_Enum; 159 160 /* ============================================= MEC_WKTMR SWCR SUBSRC [7..9] ============================================= */ 161 typedef enum { /*!< MEC_WKTMR_SWCR_SUBSRC */ 162 MEC_WKTMR_SWCR_SUBSRC_DIS = 0, /*!< DIS : Disable */ 163 MEC_WKTMR_SWCR_SUBSRC_SUBSEC = 1, /*!< SUBSEC : Sub-week counter uses sub-second as clock source */ 164 MEC_WKTMR_SWCR_SUBSRC_SEC = 2, /*!< SEC : Sub-week counter uses second as clock source */ 165 MEC_WKTMR_SWCR_SUBSRC_WKB3 = 4, /*!< WKB3 : Sub-week counter uses week counter bit[3] as clock source */ 166 MEC_WKTMR_SWCR_SUBSRC_WKB5 = 5, /*!< WKB5 : Sub-week counter uses week counter bit[5] as clock source */ 167 MEC_WKTMR_SWCR_SUBSRC_WKB7 = 6, /*!< WKB7 : Sub-week counter uses week counter bit[7] as clock source */ 168 MEC_WKTMR_SWCR_SUBSRC_WKB9 = 7, /*!< WKB9 : Sub-week counter uses week counter bit[9] as clock source */ 169 } MEC_WKTMR_SWCR_SUBSRC_Enum; 170 171 /** @} */ /* End of group EnumValue_peripherals */ 172 173 #endif /* _MEC5_WKTMR_BGPO_V1_H */ 174
