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/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dinit_mc_denali.S63 lw a0, 0x0c(a1)
64 ins a0, zero, 16, 1 # Clear Start bit
65 sw a0, 0x0c(a1)
69 li a0, 0x00000100
70 sw a0, 0x04(a1)
71 li a0, 0x00000001
72 sw a0, 0x0c(a1)
73 li a0, 0x01000101
74 sw a0, 0x10(a1)
75 li a0, 0x02020200
[all …]
Dinit_gic.S63 lw a0, 0(a1)
64 ext a0, a0, GIC_EX, GIC_EX_S // Isolate GCR_GIC_STATUS[GIC_EX].
65 beqz a0, done_gic // If no gic then skip.
72 li a0, GIC_P_BASE_ADDR | 1 // Physical address + enable bit
73 sw a0, 0(a1)
77 lw a0, GIC_SH_CONFIG(a1) // GIC_SH_CONFIG
78 ext a0, a0, NUMINTERRUPTS, NUMINTERRUPTS_S // NUMINTERRUPTS (actually slices - 1)
80 beq a0, a3, configure_slices
87 li a0, 0xff000000
88 sw a0, GIC_SH_RMASK31_0(a1) // (disable 0..31)
[all …]
Dinit_cm.S62 li a0, 2 // Start building mask for cores in this cps.
63 sll a0, a0, r19_more_cores
64 addiu a0, -1 // Complete mask.
65 sw a0, GCR_ACCESS(r22_gcr_addr) // GCR_ACCESS
68 lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
69 ext a0, a0, NUMIOCU, NUMIOCU_S // Extract NUMIOCU.
70 beqz a0, done_cm_init
71 lui a0, 0xffff
74 sw a0, GCR_REG0_BASE(r22_gcr_addr) // GCR_REG0_BASE
75 sw a0, GCR_REG0_MASK(r22_gcr_addr) // GCR_REG0_MASK
[all …]
Dset_gpr_boot_values.S70 mfc0 a0, C0_EBASE // Read CP0 EBase
71 ext r23_cpu_num, a0, 0, 4 // Extract CPUNum
78 mfc0 a0, C0_CONFIG1 // C0_Config1
79 bgez a0, no_mt_ase // bit 31 sign bit set?
80 mfc0 a0, C0_CONFIG2 // C0_Config2
81 bgez a0, no_mt_ase // bit 31 sign bit set?
82 mfc0 a0, C0_CONFIG3 // C0_Config3
83 and a0, (1 << 2) // M_Config3MT
84 beqz a0, no_mt_ase
91 mfc0 a0, C0_TCBIND // Read CP0 TCBind
[all …]
Dinit_L23caches.S75 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
77 ins a0, a3, 0, 8 // Insert bits
78 sw a0, 0x0008(r22_gcr_addr) // Write GCR_BASE
85 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
86 ext a0, a0, 4, 1 // Extract CCA_Override_Enable
87 bnez a0, done_l23 // Skip uncached execution if CCA
108 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
110 ext a0, a0, 4, 1 // Extract CCA_Override_Enable bit
115 beqz a0, done_l23
136 ext a0, v0, 8, 4 // extract SS
[all …]
Drelease_mp.S66 move a0, a3
67 sll a0, 16
68 sw a0, (CPS_CORE_LOCAL_CONTROL_BLOCK | CPC_OTHERL_REG)(r30_cpc_addr)
69 li a0, PWR_UP // "PwrUp" power domain command.
70 sw a0, (CPS_CORE_OTHER_CONTROL_BLOCK | CPC_CMDO_REG)(r30_cpc_addr)
79 move a0, a3
80 sll a0, 16
81 sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER
Djoin_domain.S64 li a0, 0x0f // Set Coherent domain enable for 4 cores
65 sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_COHERENCE)(r22_gcr_addr) // GCR_CL_COHERENCE
73 sll a0, a3, 16
74 sw a0, (CORE_LOCAL_CONTROL_BLOCK | GCR_CL_OTHER)(r22_gcr_addr) // GCR_CL_OTHER[CoreNum]
77 lw a0, (CORE_OTHER_CONTROL_BLOCK | GCR_CO_COHERENCE)(r22_gcr_addr) // GCR_CO_COHERENCE
78 beqz a0, busy_wait_coherent_core // Busy wait on cores joining.
Dinit_cpc.S61 lw a0, GCR_CPC_STATUS(r22_gcr_addr) // Read GCR_CPC_STATUS
62 andi a0, 1 // CPC_EX is bit 0
63 beqz a0, done_init_cpc // Skip if CPC is not implemented (CPC_EX not set)
66 li a0, CPC_P_BASE_ADDR // Locate CPC at same location YAMON does.
67 sw a0, GCR_CPC_BASE(r22_gcr_addr) // Write CPC_BASE address to GCR
Dstart.S172 mfc0 a0, C0_CONFIG // Read CP0 Config
173 srl a0, 10 // Shift [AT AR] into LSBs.
174 andi a3, a0, 0x18 // Inspect CP0 Config[AT]
176 andi a3, a0, 0x07 // Inspect CP0 Config[AR]
227 mfc0 a0, $0, 1 // MVPControl
228 ext a0, a0, 3, 1 // MVPControl[STLB]
229 beq a0, zero, done_tlb // TLB shared?
424 move a0, r23_cpu_num // main(arg0) is the "cpu" number (cp0 EBase[CPUNUM].)
446 ll a0, 0(a1)
447 addiu a0, a0, 1
[all …]
Dinit_tlb.S73 li a0, 0x80000000
77 mtc0 a0, C0_ENTRYHI // write C0_EntryHi
80 add a0, (2<<13) // Add 8K to the address to avoid TLB conflict with previous entry
Dinit_caches2.S140 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
142 ins a0, a3, 0, 8 // Insert bits
143 sw a0, 0x0008(r22_gcr_addr) // Write GCR_BASE
229 lw a0, 0x0008(r22_gcr_addr) // GCR_BASE
230 ins a0, zero, 0, 8 // CCA Override disabled
231 sw a0, 0x0008(r22_gcr_addr) // GCR_BASE
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_mc_denali.mip63 lw a0, 0x0c(a1)
64 ins a0, zero, 16, 1 # Clear Start bit
65 sw a0, 0x0c(a1)
69 li a0, 0x00000100
70 sw a0, 0x04(a1)
71 li a0, 0x00000001
72 sw a0, 0x0c(a1)
73 li a0, 0x01000101
74 sw a0, 0x10(a1)
75 li a0, 0x02020200
[all …]
Dinit_gic.mip63 lw a0, 0(a1)
64 ext a0, a0, GIC_EX, GIC_EX_S // Isolate GCR_GIC_STATUS[GIC_EX].
65 beqz a0, done_gic // If no gic then skip.
72 li a0, GIC_P_BASE_ADDR | 1 // Physical address + enable bit
73 sw a0, 0(a1)
77 lw a0, GIC_SH_CONFIG(a1) // GIC_SH_CONFIG
78 ext a0, a0, NUMINTERRUPTS, NUMINTERRUPTS_S // NUMINTERRUPTS (actually slices - 1)
80 beq a0, a3, configure_slices
87 li a0, 0xff000000
88 sw a0, GIC_SH_RMASK31_0(a1) // (disable 0..31)
[all …]
Dinit_cm.mip62 li a0, 2 // Start building mask for cores in this cps.
63 sll a0, a0, r19_more_cores
64 addiu a0, -1 // Complete mask.
65 sw a0, GCR_ACCESS(r22_gcr_addr) // GCR_ACCESS
68 lw a0, GCR_CONFIG(r22_gcr_addr) // Load GCR_CONFIG
69 ext a0, a0, NUMIOCU, NUMIOCU_S // Extract NUMIOCU.
70 beqz a0, done_cm_init
71 lui a0, 0xffff
74 sw a0, GCR_REG0_BASE(r22_gcr_addr) // GCR_REG0_BASE
75 sw a0, GCR_REG0_MASK(r22_gcr_addr) // GCR_REG0_MASK
[all …]
Dset_gpr_boot_values.mip70 mfc0 a0, C0_EBASE // Read CP0 EBase
71 ext r23_cpu_num, a0, 0, 4 // Extract CPUNum
78 mfc0 a0, C0_CONFIG1 // C0_Config1
79 bgez a0, no_mt_ase // bit 31 sign bit set?
80 mfc0 a0, C0_CONFIG2 // C0_Config2
81 bgez a0, no_mt_ase // bit 31 sign bit set?
82 mfc0 a0, C0_CONFIG3 // C0_Config3
83 and a0, (1 << 2) // M_Config3MT
84 beqz a0, no_mt_ase
91 mfc0 a0, C0_TCBIND // Read CP0 TCBind
[all …]
Dinit_L23caches.mip75 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
77 ins a0, a3, 0, 8 // Insert bits
78 sw a0, 0x0008(r22_gcr_addr) // Write GCR_BASE
85 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
86 ext a0, a0, 4, 1 // Extract CCA_Override_Enable
87 bnez a0, done_l23 // Skip uncached execution if CCA
108 lw a0, 0x0008(r22_gcr_addr) // Read GCR_BASE
110 ext a0, a0, 4, 1 // Extract CCA_Override_Enable bit
115 beqz a0, done_l23
136 ext a0, v0, 8, 4 // extract SS
[all …]
/ThreadX-v6.4.1/ports/xtensa/xcc/src/
Dxtensa_vectors.S154 rsr a0, EPC_1 + \level - 1 /* return address */
156 or a0, a0, a4 /* set top 2 bits */
157 addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */
312 addi a4, a0, -3 /* point to call0 */
405 wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* save original a0 somewhere */
453 wsr a0, EXCSAVE_1 /* preserve a0 */
484 wsr a0, EXCSAVE_1 /* preserve a0 */
533 rsr a0, EXCCAUSE
534 beqi a0, EXCCAUSE_LEVEL1_INTERRUPT, _xt_lowint1
540 bgeui a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
[all …]
Dtx_thread_context_save.S99 mov a12, a0 /* a12 = save ret addr (free a0) */
100 l32i a0, a13, 0 /* increment interrupt nesting count */
101 addi a0, a0, 1
102 s32i a0, a13, 0
103 bnei a0, 1, .L_tx_thread_nested_save /* was !=0 before increment? */
114 movi a0, _tx_thread_current_ptr
115 l32i a13, a0, 0 /* a13 = current thread ctrl blk */
139 mov a0, a12 /* retrieve return address */
150 mov a0, a12 /* retrieve return address */
Dtx_thread_system_return.S85 s32i a0, sp, 0 /* save return address */
120 movi a0, .Lret
123 s32i a0, sp, XT_STK_PC /* save return PC */
162 movi a0, _xt_dispatch + 3 /* Jump to dispatch code */
184 l32i a0, sp, 0
188 l32i a0, sp, 0
195 s32i a0, sp, XT_STK_PC
208 mov a4, a0 // save a0
214 l32i a0, sp, XT_STK_PS
215 wsr a0, PS // Restore PS value
[all …]
Dtx_thread_schedule.S88 movi a0, _xt_dispatch + 3 /* Jump to dispatch code. It will */
141 l32i a0, a2, tx_thread_run_count
146 addi a3, a0, 1
147 movi a0, _tx_timer_time_slice
153 s32i a3, a0, 0
159 movi a0, _impure_ptr
161 movi a0, _reent_ptr
167 s32i a3, a0, 0 /* point to thread's reent struct */
215 l32i a0, sp, XT_STK_EXIT
221 movi a0, TX_FALSE
[all …]
Dxtensa_coproc_handler.S103 mov a7, a0 // a7 = return address
113 movi a0, _xt_coproc_mask
115 addx4 a0, a5, a0 // a0 = &_xt_coproc_mask[n]
116 l32i a0, a0, 0 // a0 = (n << 16) | (1 << n)
118 extui a2, a0, 0, 16 // coprocessor bitmask portion
136 bnone a4, a0, .L_check_new // old owner not using CP
143 xor a4, a4, a0 // clear CP in old owner's CPENABLE
146 extui a4, a0, 16, 5 // a4 = CP index = n
152 or a4, a4, a0 // set CP in old owner's CPSTORED
155 extui a3, a0, 16, 5 // a3 = CP index = n
[all …]
Dxtensa_vectors_xea3.S127 movi a0, 0
128 l32dis.it a0, a0 // a0 <- wrapper addr (handler_table[0])
133 s32dis.h a0, a0 // Jump to handler if interrupt else fall through
173 s32e a0, a1, -64 // [a1-64] <- a0
234 movi a0, 0
235 l32dis.it a0, a0 // a0 <- wrapper addr (handler_table[0])
240 s32dis.h a0, a0 // Jump to handler if interrupt else fall through
316 l32e a0, a1, -64 // a0 <- [a1-64]
Dtx_thread_context_restore.S84 XT_INTS_DISABLE(a0)
115 movi a0, _tx_thread_current_ptr /* a0 = &_tx_thread_current_ptr */
116 l32i a2, a0, 0 /* a2 = _tx_thread_current_ptr (old) */
168 s32i a4, a0, 0 /* a4 == 0 == TX_NULL */
211 l32i a0, sp, XT_STK_EXIT
/ThreadX-v6.4.1/ports/risc-v64/gnu/src/
Dtx_thread_interrupt_control.S77 or t0, t0, a0 // Put new lockout bits in
79 andi a0, t1, RETURN_MASK // Return original mstatus.
/ThreadX-v6.4.1/ports/risc-v32/iar/src/
Dtx_thread_interrupt_control.s87 or t0, t0, a0 ; Put new lockout bits in
89 andi a0, t1, RETURN_MASK ; Return original mstatus.

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