1/***************************************************************************
2 * Copyright (c) 2024 Microsoft Corporation
3 *
4 * This program and the accompanying materials are made available under the
5 * terms of the MIT License which is available at
6 * https://opensource.org/licenses/MIT.
7 *
8 * SPDX-License-Identifier: MIT
9 **************************************************************************/
10
11/**************************************************************************/
12/*   Copyright (c) Cadence Design Systems, Inc.                           */
13/*                                                                        */
14/* Permission is hereby granted, free of charge, to any person obtaining  */
15/* a copy of this software and associated documentation files (the        */
16/* "Software"), to deal in the Software without restriction, including    */
17/* without limitation the rights to use, copy, modify, merge, publish,    */
18/* distribute, sublicense, and/or sell copies of the Software, and to     */
19/* permit persons to whom the Software is furnished to do so, subject to  */
20/* the following conditions:                                              */
21/*                                                                        */
22/* The above copyright notice and this permission notice shall be         */
23/* included in all copies or substantial portions of the Software.        */
24/*                                                                        */
25/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
26/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
27/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
28/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
29/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
30/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
31/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
32/**************************************************************************/
33
34/**************************************************************************/
35/**************************************************************************/
36/**                                                                       */
37/** ThreadX Component                                                     */
38/**                                                                       */
39/**   Thread                                                              */
40/**                                                                       */
41/**************************************************************************/
42/**************************************************************************/
43
44#include "xtensa_rtos.h"
45#include "tx_api_asm.h"
46
47
48#if XCHAL_HAVE_XEA2
49
50    .text
51
52/**************************************************************************/
53/*                                                                        */
54/*  DESCRIPTION                                                           */
55/*                                                                        */
56/*    This function saves the context of an executing thread in the       */
57/*    beginning of interrupt processing.  The function also ensures that  */
58/*    the system stack is used upon return to the calling ISR.            */
59/*                                                                        */
60/*    Interrupts remain disabled and no exceptions are triggered!         */
61/*                                                                        */
62/*  RELEASE HISTORY                                                       */
63/*                                                                        */
64/*    DATE              NAME                      DESCRIPTION             */
65/*                                                                        */
66/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
67/*                                                                        */
68/**************************************************************************/
69
70//  VOID   _tx_thread_context_save(VOID)
71//  {
72    .globl  _tx_thread_context_save
73    .type   _tx_thread_context_save,@function
74    .align  4
75_tx_thread_context_save:
76
77    /*
78    Please note: Control flow might seem strange. This is because it has been
79    optimized to avoid taken branches in the longest normal path (the critical
80    one for worst-case latency), presumed to be a non-nested interrupt and
81    non-idle) and to hide pipeline interlock cycles where possible.
82    */
83
84    /*
85    Save a couple of scratch regs to work with that are preserved over the
86    call to _xt_context_save. The latter assumes the interruptee's values
87    of these are already saved and these regs contain different data to be
88    preserved, so doesn't save them in the stack frame, and thereby requires
89    that its caller have already saved them in the interrupt stack frame.
90    We end up with a12 = return address, a13 and a0 are scratch.
91    */
92    s32i    a12, sp, XT_STK_A12
93    s32i    a13, sp, XT_STK_A13
94
95    /* Check for a nested interrupt condition and increment nesting count.  */
96    //  if (_tx_thread_system_state++)
97    //  {
98    movi    a13, _tx_thread_system_state /* a13 = & interrupt nesting count */
99    mov     a12, a0                      /* a12 = save ret addr (free a0) */
100    l32i    a0,  a13, 0                  /* increment interrupt nesting count */
101    addi    a0,  a0,  1
102    s32i    a0,  a13, 0
103    bnei    a0,  1,   .L_tx_thread_nested_save  /* was !=0 before increment? */
104
105    //  }
106
107.Ln_tx_thread_not_nested_save:
108
109    /* Otherwise, not nested, check to see if a thread was running. */
110    //  else
111    //  {
112    //      if (_tx_thread_current_ptr)
113    //      {
114    movi    a0,  _tx_thread_current_ptr
115    l32i    a13, a0,  0                  /* a13 = current thread ctrl blk */
116    beqz    a13, .L_tx_thread_idle_system_save
117
118    /* Save the rest of the interrupted context. */
119    call0   _xt_context_save
120
121    /* Save the current stack pointer in the thread's control block. */
122    //          _tx_thread_current_ptr -> tx_thread_stack_ptr =  sp;
123    s32i    sp,  a13, tx_thread_stack_ptr
124
125    //      }
126    /* Switch to the system stack and return to ISR. */
127
128.L_tx_thread_idle_system_save:
129
130    /*
131    If interrupted in the idle state, it's not necessary to save any context.
132    But even in the idle case where we are already on the system stack, it is
133    necessary to reset the (system) stack pointer so a series of consecutive
134    interrupts in the idle state do not keep moving the SP downward.
135    */
136
137    //      sp =  _tx_thread_system_stack_ptr;
138    movi    a13, _tx_thread_system_stack_ptr
139    mov     a0,  a12                     /* retrieve return address */
140    l32i    sp,  a13, 0
141
142    ret
143    //  }
144
145.L_tx_thread_nested_save:
146    /* Nested interrupt condition. */
147    /* Save the rest of the interrupted context and return to ISR. */
148    call0   _xt_context_save
149
150    mov     a0,  a12                     /* retrieve return address */
151    ret
152
153//  }
154
155#endif /* XCHAL_HAVE_XEA2 */
156
157