1/*
2 * init_L23caches.S
3 *
4 *  Created on: Jun 8, 2012
5 *      Author: chrisr
6 */
7/*
8Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.  Unpublished rights reserved
9under the copyright laws of the United States of America and other countries.
10
11This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
12may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
13Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
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17
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33This code may only be disclosed to the United States government ("Government"), or to
34Government users, with prior written consent from MIPS Technologies or an authorized third
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36commercial computer software documentation or other commercial items.  If the user of this
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45*/
46
47#include <boot.h>
48#include <mips/regdef.h>
49#include <mips/m32c0.h>
50	.set	noreorder           // Don't allow the assembler to reorder instructions.
51	.set	noat                // Don't allow the assembler to use r1(at) for synthetic instr.
52
53/**************************************************************************************
54**************************************************************************************/
55/**************************************************************************************
56* Initialize the L2 and L3 caches Uncached version no CPS
57**************************************************************************************/
58LEAF(init_l23u)
59
60    // Use CCA Override disable the L2 cache or initialize the L2
61    // and L3 caches if CCA override is not available.
62    // NOTE: If you have a L3 cache you must add code here
63    // to disable it or initialize it if it can't be disabled.
64
65    // First check to see if this is a CPS, if not
66    // the l2 CCA override is not present and the L2 will have to be initialized
67    // from uncached code.
68    beqz    r11_is_cps, init_l23
69    nop
70
71    // Diaable the L2 cache using CCA override by writting a 0x50 to
72    // the GCR Base register. 0x50 enables the CCA override bit and sets
73    // the CCA to uncached.
74
75	lw	    a0, 0x0008(r22_gcr_addr)  // Read GCR_BASE
76    li      a3, 0x50                  // Enable CCA and set to uncached
77    ins     a0, a3, 0, 8    // Insert bits
78    sw      a0, 0x0008(r22_gcr_addr)  // Write GCR_BASE
79
80    // Read the GCR_BASE register back to see if the enabling
81    // of the CCA override took. If it did skip the L2 and L3
82    // initialization. (It will be called later once the L1 cache has
83    // been initialized, for better performance.)
84
85	lw	    a0, 0x0008(r22_gcr_addr)  // Read GCR_BASE
86    ext     a0, a0, 4, 1    // Extract CCA_Override_Enable
87    bnez    a0, done_l23          	// Skip uncached execution if CCA
88    											// Override is implemented.
89    nop
90
91    // If the code gets here the CCA override is not available so
92    // the L2 cache can't be disabled and must be initialized now
93    // instead of later.
94    b		init_l23
95    nop
96END(init_l23u)
97/**************************************************************************************
98* Initialize the L2 and L3 caches cached version is CPS
99**************************************************************************************/
100LEAF(init_l23c)
101
102    // Skip cached execution if CCA Override is not implemented.
103    // If CCA override is not implemented the L2 and L3 caches
104    // would have already been initialized when init_l23u was called.
105
106    beqz    r11_is_cps, done_l23
107    nop
108	lw	    a0, 0x0008(r22_gcr_addr)  // Read GCR_BASE
109    bnez    r8_core_num, done_l23			    // Check it for Core0.
110    ext     a0, a0, 4, 1    // Extract CCA_Override_Enable bit
111
112    // If CCA override is not set it means that the setting failed in
113    // init_l23u and the L2 and L3 caches were initialized at that time
114    // If it is set then the code will fall through and initialize the L2/L3 caches
115    beqz    a0, done_l23
116    nop
117END(init_l23c)
118
119LEAF(init_l23)
120	// L2 Cache initialization routine
121
122	// Check L2 cache size
123	mfc0	v0, C0_CONFIG2		// C0_Config2
124
125	// Isolate L2$ Line Size
126	ext	    v1, v0, 4, 4		// extract SL
127
128	// Skip ahead if No L2$
129	beq	    v1, zero, done_l2cache
130	nop
131
132	li	    a2, 2
133	sllv	v1, a2, v1		// Now have true L2$ line size in bytes
134
135	// Isolate L2$ Sets per Way
136	ext	    a0, v0, 8, 4		// extract SS
137	li	    a2, 64
138	sllv	a0, a2, a0		// L2$ Sets per way
139
140	// Isolate L2$ Associativity
141	// L2$ Assoc (-1)
142	ext	    a1, v0, 0, 4		// extract SA
143	add	    a1, 1
144
145	mul	    a0, a0, a1		// Get total number of sets
146
147	lui	    a2, 0x8000		// Get a KSeg0 address for cacheops
148
149	// Clear L23TagLo/L23TagHi registers
150	mtc0	zero, C0_TAGLO, 4
151
152	move	a3, a0
153
154	// L2$ Index Store Tag Cache Op
155	// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
156next_L2cache_tag:
157	cache	0xB, 0(a2)					// Write Tag using index store tag
158	add	    a3, -1						// Decrement set counter
159
160	bne	    a3, zero, next_L2cache_tag 	// Done yet?
161	add	    a2, v1						// Get next line address
162
163done_l2cache:
164
165	// Isolate L3$ Line Size
166	ext	    v1, v0, CFG2_TLSHIFT, 4		// Extract L3 line size
167
168	// Skip ahead if No L3$
169	beq	    v1, zero, done_l3cache
170	nop
171
172	li	    a2, 2
173	sllv	v1, a2, v1					// Decode L3$ line size in bytes
174
175	// Isolate L3$ Sets per Way
176	ext	    a0, v0, CFG2_TSSHIFT, 4		// Extract L3 sets per way TDS encoding
177	li	    a2, 64
178	sllv	a0, a2, a0		// Decode L3 Sets per way
179
180	// Isolate L3$ Associativity
181	// L3$ Assoc (-1)
182	ext	    a1, v0, CFG2_TASHIFT, 4		// Extrace L3 associativity 2TA encoding
183	add	    a1, 1						// Decode L3 associativity (number of sets)
184	mul	    a0, a0, a1					// Compute total number of sets
185
186	lui	    a2, 0x8000		   			// Get a KSeg0 address for cacheops
187
188	// Clear L23Tag register
189	mtc0	zero, C0_TAGLO, 4
190
191
192	move	a3, a0
193
194	// L3$ Index Store Tag Cache Op
195	// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
196next_L3cache_tag:
197	cache	0xA, 0(a2)					// TCIndexStTag
198	add	    a3, -1						// Decrement set counter
199	bne	    a3, zero, next_L3cache_tag
200	add	    a2, v1						// Get next line address
201
202done_l3cache:
203    // disable CCA Override
204    beqz    r11_is_cps, done_l23
205    nop
206	lw	    a0, 0x0008(r22_gcr_addr)  	// GCR_BASE
207    ins     a0, zero, 0, 8    			// CCA Override disabled
208    sw      a0, 0x0008(r22_gcr_addr)  	// GCR_BASE
209
210done_l23:
211    jr      ra
212    nop
213END(init_l23)
214
215
216