Home
last modified time | relevance | path

Searched refs:bits (Results 1 – 20 of 20) sorted by relevance

/Renode-v1.15.3-c57714d/tests/unit-tests/
Driscv-zve-extension.robot6 ${bits}= Set Variable 32
8 ${bits}= Set Variable 64
14 …Execute Command machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV${bits} @…
Driscv-custom-instructions.robot57 …Run Keyword And Expect Error *Pattern 0xB38F is invalid for 16 bits long instructio…
61 …Run Keyword And Expect Error *Pattern 0xB38F0F82 is invalid for 32 bits long instru…
64 …Run Keyword And Expect Error *Pattern 0xB38F0F9F is invalid for 32 bits long instru…
67 …Run Keyword And Expect Error *Pattern 0xB38F0F9E is invalid for 32 bits long instru…
71 …Run Keyword And Expect Error *Pattern 0xB38F0F82B38F0FBB is invalid for 64 bits lon…
74 …Run Keyword And Expect Error *Pattern 0xB38F0F82B38F0FFF is invalid for 64 bits lon…
Dit-status.robot179 …The a, b, c, d, and e bits encode the number of instructions that are to be conditionally executed…
181 …When an IT instruction is executed, these bits are set according to the condition in the instructi…
182 …During execution of an IT block, the a, b, c, d, and e bits are shifted left after every instructi…
186 …To encode condition on 3 bits we omit last bit which always means reversing the condition, and neg…
223 Should Contain ${it} 0x00000005 # IT_cond = 0b000; abcde bits = 0b00101
231 Should Contain ${it} 0x000000AD # IT_cond = 0b101; abcde bits = 0b00101
334 Should Contain ${it} 0x00000005 # IT_cond = 0b000; abcde bits = 0b00101
340 Should Contain ${it} 0x0000000A # IT_cond = 0b000; abcde bits = 0b01010
346 Should Contain ${it} 0x00000014 # IT_cond = 0b000; abcde bits = 0b10100
352 Should Contain ${it} 0x00000008 # IT_cond = 0b000; abcde bits = 0b01000
[all …]
DARMv8R_TCM.robot67 "TCMTR" 0 0b111 0b111 ABC enabled region bits incorrect
68 "TCMTR" 29 0b1111 0b100 TCM bits incorrect
Darm-signals-unit.robot114 # When set from address, the signal is set to a value based on address' top bits.
125 …# Setting signals from addresses with bits over 32 set is invalid for Cortex-R8 even though only t…
134 …# PFILTERSTART is a 12-bit signal so setting it from an address with any of bits 0-19 set should f…
291 # Base can be up to 20 bits.
296 # Size can be up to 5 bits.
Dbus-isolation.robot129 … but the initiator 'reader2' doesn't implement IPeripheralWithTransactionState or has no state bits
150 …e are no peripherals implementing IPeripheralWithTransactionState or they have no common state bits
Darm-performance-monitoring-unit.robot562 # Peripheral ID's bits 20-23 should contain variant from bits 20-23 of MIDR.
565 # Each of PMPID0-PMPID7 contains 8 bits from PeripheralId.
/Renode-v1.15.3-c57714d/src/Plugins/CoSimulationPlugin/IntegrationLibrary/src/buses/
Dwishbone-initiator.h68 constexpr size_t bits = 8; in readWord() local
69 for (size_t i = 0; i < bits; i++) in readWord()
112 constexpr size_t bits = 8; in writeWord() local
113 for (size_t i = 0; i < bits; i++) in writeWord()
/Renode-v1.15.3-c57714d/tests/peripherals/CLIC/
DCLIC-mcause-mstatus-alias.robot5 # and write to MSTATUS to check if bits are mirrored in MCAUSE
13 # and write to MCAUSE to check if bits are mirrored in MSTATUS
20 # Same as above, but CLINT mode, so bits should not be mirrored
/Renode-v1.15.3-c57714d/tests/peripherals/
DMC3635.robot77 …Wait For Log Entry Invalid value written to offset 0x20 reserved bits. Allowed values = 0b0…
79 …Wait For Log Entry Invalid value written to offset 0x21 reserved bits. Allowed values = 0b1…
81 …Wait For Log Entry Invalid value written to offset 0x22 reserved bits. Allowed values = 0b0…
DLIS2DW12.robot49 Fail Invalid resolution ${resolution} bits
/Renode-v1.15.3-c57714d/platforms/cpus/
Dstm32l552.repl113 // Hard set all oscillator RDY bits
Dstm32l151.repl152 // Hard set all oscillator RDY bits
Dambiq-apollo4.repl99 …// The last 6 bits contain the fraction part in measurement averages computed from multiple sample…
/Renode-v1.15.3-c57714d/tests/platforms/LiteX/
DLiteX_Linux_VexRiscv.robot91 Wait For Line On Uart bits per word: 8
/Renode-v1.15.3-c57714d/tools/PeakRDL-renode/
DREADME.md205 Fields wider than 64 bits are not supported.
/Renode-v1.15.3-c57714d/tests/platforms/
DOpenTitan-EarlGrey.robot136 # B is 0100 0010. Take the lower 4 bits.
/Renode-v1.15.3-c57714d/images/
Drenode-screencast.svg190 …bits: [2] when writing value 0.</text></g><g id="g307"><text x="0" textLength="312" class="foregro…
/Renode-v1.15.3-c57714d/src/Plugins/CoSimulationPlugin/IntegrationLibrary/libs/socket-cpp/
DREADME.md203 …an download and install OpenSSL : https://slproweb.com/products/Win32OpenSSL.html (32 and 64 bits).
/Renode-v1.15.3-c57714d/
DCHANGELOG.rst18 * added ability to configure usable bits in RISC-V PMPADDR registers
403 * RISC-V xRET instructions not changing status bits correctly
1237 * added GDB support for VS bits in MSTATUS register
1239 * added support for CPU registers wider than 64-bits in Renode (C# part, not tlibs)
2075 * timers can now hold values up to 64 bits