1*** Comments *** 2Tests for OpenTitan at commit f243e6802143374741739d2c164c4f2f61697669 3 4*** Variables *** 5${UART} sysbus.uart0 6${AES_BIN} @https://dl.antmicro.com/projects/renode/aes_smoketest_prog_fpga_cw310.elf-s_325384-ef59f6e8ac7f56e8f3ee0f151652464a95023ad7 7${CSRNG_BIN} @https://dl.antmicro.com/projects/renode/csrng_smoketest_prog_fpga_cw310.elf-s_336108-1a49396335efc0975ac5d4d99241028bb4711419 8${FLASH_CTRL_BIN} @https://dl.antmicro.com/projects/renode/flash_ctrl_test_prog_fpga_cw310.elf-s_424784-c8fa392bab21661e29224b2ee8678076502aa242 9${GPIO_BIN} @https://dl.antmicro.com/projects/renode/gpio_smoketest_prog_fpga_cw310.elf-s_362872-de8f5853a07e44dd8ba55651d5293bd33f9b66d6 10${HMAC_BIN} @https://dl.antmicro.com/projects/renode/hmac_smoketest_prog_fpga_cw310.elf-s_323008-274f6dd2f28ca66f6baa1be5304497c0ce7b6201 11${KMAC_BIN} @https://dl.antmicro.com/projects/renode/kmac_smoketest_prog_fpga_cw310.elf-s_347412-b12dd1cc85f45d1e3256613441c41afe2ed127f0 12${KMAC_CSHAKE_BIN} @https://dl.antmicro.com/projects/renode/kmac_mode_cshake_test_prog_fpga_cw310.elf-s_334036-371c0b874622b5468d391bf76c2d4494a2621020 13${KMAC_KMAC_BIN} @https://dl.antmicro.com/projects/renode/kmac_mode_kmac_test_prog_fpga_cw310.elf-s_336072-7200324f9eb2f9feba7b3c9d0a99e8faaf0b118c 14${LC_OTP_CFG} @https://dl.antmicro.com/projects/renode/lc_ctrl_otp_hw_cfg_test_prog_fpga_cw310.elf-s_351476-97168d00236be711f39cd24ec343b8ee593852ef 15${OTP_VMEM} @https://dl.antmicro.com/projects/renode/otp_img_fpga_cw310.vmem-s_49520-971ccda1d11a9f0c690f4f32b72f1b5f3b458059 16${RESET_BIN} @https://dl.antmicro.com/projects/renode/rstmgr_smoketest_prog_fpga_cw310.elf-s_288244-c3d023ac96dc447e626ead042e1d8337d5ceaee6 17${SW_RESET_BIN} @https://dl.antmicro.com/projects/renode/rstmgr_sw_req_test_prog_fpga_cw310.elf-s_306308-2cc96fe5320d0c1b54153ddc6506e09d90133917 18${TEST_ROM} @https://dl.antmicro.com/projects/renode/test_rom_fpga_cw310.elf-s_447072-1cdfd7b2a98b0c09f158d8267c5e9fbbf34dd33b 19${TEST_ROM_SCR_VMEM} @https://dl.antmicro.com/projects/renode/test_rom_fpga_cw310.39.scr.vmem-s_103772-d3a8f17879eedbcbf18e554bfd7871ccd992414e 20${TIMER_BIN} @https://dl.antmicro.com/projects/renode/rv_timer_smoketest_prog_fpga_cw310.elf-s_310476-ace649750b26ef6ae36c099bf777fe280212ef21 21${UART_BIN} @https://dl.antmicro.com/projects/renode/uart_smoketest_prog_fpga_cw310.elf-s_282560-87570a6fcb3684b126ef3c0ca9bfd53a0dc68936 22${ALERT_HANDLER} @https://dl.antmicro.com/projects/renode/alert_test_prog_fpga_cw310.elf-s_681764-d7203f6da5d986ce9a57d641ff1261a450a4c63d 23${ALERT_HANDLER_PING} @https://dl.antmicro.com/projects/renode/alert_handler_ping_timeout_test_prog_fpga_cw310.elf-s_484472-9abdc0b5e973cde8b9746d2e8ec8a997dbc8d0ba 24${SPI_HOST} @https://dl.antmicro.com/projects/renode/spi_host_smoketest_prog_fpga_cw310.elf-s_321216-41ad0ca0446549371d07b4d8209ddfbc08c8be33 25${AON_TIMER_IRQ_BIN} @https://dl.antmicro.com/projects/renode/aon_timer_irq_test_prog_fpga_cw310.elf-s_388756-3411f90c38a58858140ae754bc06d7b6c2c2eff5 26${AON_TIMER_WDOG_SLEEP_BIN} @https://dl.antmicro.com/projects/renode/aon_timer_sleep_wdog_sleep_pause_test_prog_fpga_cw310.elf-s_373448-c0d65458130e457165e7575712a0ccb66ad27f80 27${AON_TIMER_BIN} @https://dl.antmicro.com/projects/renode/aon_timer_smoketest_prog_fpga_cw310.elf-s_317844-46f92ea7a8772be2afcf695e7fdb9df44216c852 28${AON_TIMER_WDOG_BITE_BIN} @https://dl.antmicro.com/projects/renode/aon_timer_wdog_bite_reset_test_prog_fpga_cw310.elf-s_371232-16ea5f84891ef4973add5fcf42b3e7fb9eb236d2 29${ENTROPY_SRC_AST_REQ_BIN} @https://dl.antmicro.com/projects/renode/entropy_src_ast_rng_req_test_prog_fpga_cw310.elf-s_322228-5d384e67d50472d80b8d66cf180ceb3b71e5ab15 30${ENTROPY_SRC_FW_OVR_BIN} @https://dl.antmicro.com/projects/renode/entropy_src_fw_ovr_test_prog_fpga_cw310.elf-s_347200-0e9636ca3c57e66a7a471143a0c48012d2c3753f 31${ENTROPY_SRC_KAT_BIN} @https://dl.antmicro.com/projects/renode/entropy_src_kat_test_prog_fpga_cw310.elf-s_391260-76d830cb1746909c033f1f8930cae428855b4b24 32${SRAM_CTRL_BIN} @https://dl.antmicro.com/projects/renode/sram_ctrl_smoketest_prog_fpga_cw310.elf-s_291188-63360ab9786db3a84da77b8766e458d119227dd5 33${OTBN_ECDSA_BIN} @https://dl.antmicro.com/projects/renode/otbn_ecdsa_op_irq_test_prog_fpga_cw310.elf-s_460328-d9b26904a2e79a6df89bda0d74c267351d839a2d 34${OTBN_IRQ_BIN} @https://dl.antmicro.com/projects/renode/otbn_irq_test_prog_fpga_cw310.elf-s_445860-54133c6721deb5c0ac8713a06da7f93253276f7e 35${OTBN_SCRAMBLE_BIN} @https://dl.antmicro.com/projects/renode/otbn_mem_scramble_test_prog_fpga_cw310.elf-s_357976-17001e15e1ccc12075ff0bb108b0bc8fa0a96427 36${OTBN_RAND_BIN} @https://dl.antmicro.com/projects/renode/otbn_randomness_test_prog_fpga_cw310.elf-s_481904-c61657cd5db42f70c7814644b436405610850e33 37${OTBN_SMOKETEST_BIN} @https://dl.antmicro.com/projects/renode/otbn_smoketest_prog_fpga_cw310.elf-s_444776-8169ee20540f64f867206d17a18e8de5e6270f8e 38${OTBN_RSA_BIN} @https://dl.antmicro.com/projects/renode/otbn_rsa_test_prog_fpga_cw310.elf-s_446140-6d6a4c0197d9fcc54c44cbe68db0003d7cb44783 39${OTBN_SIMPLE_SMOKETEST_BIN} @https://dl.antmicro.com/projects/renode/open_titan-earlgrey--otbn_simple_smoketest.elf-s_9164-5362a0be6d650280b2f732460e786a8d7263126b 40 41 42${LEDS}= SEPARATOR= 43... """ ${\n} 44... gpio: ${\n} 45... ${SPACE*4}0 -> led0@0 ${\n} 46... ${SPACE*4}1 -> led1@0 ${\n} 47... ${SPACE*4}2 -> led2@0 ${\n} 48... ${SPACE*4}3 -> led3@0 ${\n} 49... ${\n} 50... led0: Miscellaneous.LED @ gpio 0 ${\n} 51... led1: Miscellaneous.LED @ gpio 1 ${\n} 52... led2: Miscellaneous.LED @ gpio 2 ${\n} 53... led3: Miscellaneous.LED @ gpio 3 ${\n} 54... """ 55 56${SPI_FLASH}= SEPARATOR= 57... """ ${\n} 58... spi_flash: Memory.MappedMemory ${\n} 59... ${SPACE*4}size: 0x1000000 ${\n} 60... ${\n} 61... mt25q: SPI.Micron_MT25Q @ spi_host0 0 ${\n} 62... ${SPACE*4}underlyingMemory: spi_flash ${\n} 63... """ 64 65*** Keywords *** 66Setup Machine 67 Execute Command include @scripts/single-node/opentitan-earlgrey.resc 68 Execute Command machine LoadPlatformDescriptionFromString ${LEDS} 69 Execute Command machine LoadPlatformDescriptionFromString ${SPI_FLASH} 70 Execute Command sysbus.otp_ctrl LoadVmem ${OTP_VMEM} 71 Execute Command rom_ctrl LoadVmem ${TEST_ROM_SCR_VMEM} 72 Execute Command cpu0 PC 0x00008084 73 74 Set Default Uart Timeout 1 75 Create Terminal Tester ${UART} 76 77Prepare Test 78 [Arguments] ${bin} 79 Execute Command $bin=${bin} 80 Execute Command $boot=${TEST_ROM} 81 Setup Machine 82 83Execute Test 84 Start Emulation 85 Wait For Line On UART PASS 86 87Run Test 88 [Arguments] ${bin} 89 Prepare Test ${bin} 90 Execute Test 91 92Core Register Should Be Equal 93 [Arguments] ${idx} ${expected_value} 94 95 ${val}= Execute Command otbn GetCoreRegister ${idx} 96 Should Be Equal As Numbers ${val} ${expected_value} Register x${idx} value mismatch (actual != expected) 97 98Wide Register Should Be Equal 99 [Arguments] ${idx} ${expected_value} 100 101 ${val}= Execute Command otbn GetWideRegister ${idx} False 102 Should Be Equal ${val.strip()} ${expected_value} Register w${idx} value mismatch (actual != expected) 103 104*** Test Cases *** 105Should Print To Uart 106 Setup Machine 107 Start Emulation 108 109 Wait For Line On Uart The LEDs show the lower nibble of the ASCII code of the last character. 110 111 Provides initialization 112 113Should Echo On Uart 114 Requires initialization 115 116 Write Line To Uart Testing testing 1-2-3 117 118 Provides working-uart 119 120Should Display Output on GPIO 121 Requires working-uart 122 123 ${led0}= Create LED Tester sysbus.gpio.led0 defaultTimeout=0.2 124 ${led1}= Create LED Tester sysbus.gpio.led1 defaultTimeout=0.2 125 ${led2}= Create LED Tester sysbus.gpio.led2 defaultTimeout=0.2 126 ${led3}= Create LED Tester sysbus.gpio.led3 defaultTimeout=0.2 127 128 Send Key To Uart 0x0 129 130 Assert LED State false testerId=${led0} 131 Assert LED State false testerId=${led1} 132 Assert LED State false testerId=${led2} 133 Assert LED State false testerId=${led3} 134 135 Write Char On Uart B 136 # B is 0100 0010. Take the lower 4 bits. 137 138 Assert LED State false testerId=${led0} 139 Assert LED State true testerId=${led1} 140 Assert LED State false testerId=${led2} 141 Assert LED State false testerId=${led3} 142 143Should Pass AES Smoketest 144 Run Test ${AES_BIN} 145 146Should Pass UART Smoketest 147 Run Test ${UART_BIN} 148 149Should Pass HMAC Smoketest 150 Run Test ${HMAC_BIN} 151 152Should Pass Flash Smoketest 153 Run Test ${FLASH_CTRL_BIN} 154 155Should Pass Timer Smoketest 156 Run Test ${TIMER_BIN} 157 158Should Pass KMAC Smoketest 159 Run Test ${KMAC_BIN} 160 161Should Pass KMAC CSHAKE Mode 162 Run Test ${KMAC_CSHAKE_BIN} 163 164Should Pass KMAC KMAC Mode 165 Run Test ${KMAC_KMAC_BIN} 166 167Should Pass Reset Smoketest 168 Run Test ${RESET_BIN} 169 170Should Pass Software Reset Test 171 Run Test ${SW_RESET_BIN} 172 173Should Pass Life Cycle Smoketest 174 Run Test ${LC_OTP_CFG} 175 176Should Pass CSRNG Smoketest 177 Run Test ${CSRNG_BIN} 178 179Should Pass GPIO Smoketest 180 Run Test ${GPIO_BIN} 181 182Should Pass Alert Handler Smoketest 183 Run Test ${ALERT_HANDLER} 184 185Should Pass Alert Handler Ping Smoketest 186 Run Test ${ALERT_HANDLER_PING} 187 188Should Pass SPI Host Smoketest 189 Run Test ${SPI_HOST} 190 191Should Pass Aon Timer Interrupt Smoketest 192 Run Test ${AON_TIMER_IRQ_BIN} 193 194Should Pass Aon Timer Watchdog Sleep Pause Smoketest 195 Run Test ${AON_TIMER_WDOG_SLEEP_BIN} 196 197Should Pass Aon Timer Smoketest 198 Run Test ${AON_TIMER_BIN} 199 200Should Pass Aon Timer Watchdog Bite Reset Smoketest 201 Run Test ${AON_TIMER_WDOG_BITE_BIN} 202 203Should Try To Reset On The System Reset Control Combo 204 Setup Machine 205 Create Log Tester 0 206 Execute Command sysbus.sysrst_ctrl WriteDoubleWord 0x54 0x8 # Set combo0 to just pwrButton 207 Execute Command sysbus.sysrst_ctrl WriteDoubleWord 0x74 0x8 # Set combo0 action to rstReq 208 Execute Command sysbus.sysrst_ctrl WriteDoubleWord 0x30 0x40 # Invert the pwrButton input 209 # Expect error as this should work only when done by CPU 210 Wait For Log Entry Couldn't find the CPU requesting translation block restart. 211 Wait For Log Entry Software reset failed. 212 213Should Pass Entropy Source Analog Sensor Top Request Smoketest 214 Run Test ${ENTROPY_SRC_AST_REQ_BIN} 215 216Should Pass Entropy Source Firmware Override Smoketest 217 Run Test ${ENTROPY_SRC_FW_OVR_BIN} 218 219Should Pass Entropy Source Known Answer Test Smoketest 220 Run Test ${ENTROPY_SRC_KAT_BIN} 221 222Should Pass SRAM Controller Smoketest 223 Run Test ${SRAM_CTRL_BIN} 224 225Should Pass OTBN ECDSA Test 226 Run Test ${OTBN_ECDSA_BIN} 227 228Should Pass OTBN IRQ Test 229 Run Test ${OTBN_IRQ_BIN} 230 231Should Pass OTBN Memory Scramble Test 232 Run Test ${OTBN_SCRAMBLE_BIN} 233 234Should Pass OTBN Randomness Test 235 Run Test ${OTBN_RAND_BIN} 236 237Should Pass OTBN RSA Test 238 Run Test ${OTBN_RSA_BIN} 239 240Should Pass OTBN Smoketest Test 241 Run Test ${OTBN_SMOKETEST_BIN} 242 243Should Pass OTBN Simple Smoketest Test 244 Create Log Tester 3 245 Execute Command include @scripts/single-node/opentitan-earlgrey.resc 246 Execute Command sysbus.otbn FixedRandomPattern "0xAAAAAAAA99999999AAAAAAAA99999999AAAAAAAA99999999AAAAAAAA99999999" 247 248 Execute Command sysbus.otbn KeyShare0 "0xDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEFDEADBEEF" 249 Execute Command sysbus.otbn KeyShare1 "0xBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00DBAADF00D" 250 251 Execute Command logLevel -1 sysbus.otbn 252 253 # load program directly to OTBN 254 Execute Command sysbus.otbn LoadELF ${OTBN_SIMPLE_SMOKETEST_BIN} 255 256 # trigger execution of the program 257 Execute Command allowPrivates true 258 Execute Command sysbus.otbn HandleCommand 0xd8 259 260 # wait for the program to end 261 Wait For Log Entry Execution finished 262 263 # verify final state of registers 264 Core Register Should Be Equal 2 0xd0beb513 265 Core Register Should Be Equal 3 0xa0be911a 266 Core Register Should Be Equal 4 0x717d462d 267 Core Register Should Be Equal 5 0xcfffdc07 268 Core Register Should Be Equal 6 0xf0beb51b 269 Core Register Should Be Equal 7 0x80be9112 270 Core Register Should Be Equal 8 0x70002409 271 Core Register Should Be Equal 9 0xd0beb533 272 Core Register Should Be Equal 10 0x00000510 273 Core Register Should Be Equal 11 0xd0beb169 274 Core Register Should Be Equal 12 0xfad44c00 275 Core Register Should Be Equal 13 0x000685f5 276 Core Register Should Be Equal 14 0xffa17d6a 277 Core Register Should Be Equal 15 0x4c000000 278 Core Register Should Be Equal 16 0x00000034 279 Core Register Should Be Equal 17 0xfffffff4 280 Core Register Should Be Equal 18 0xfacefeed 281 Core Register Should Be Equal 19 0xd0beb533 282 Core Register Should Be Equal 20 0x00000123 283 Core Register Should Be Equal 21 0x00000123 284 Core Register Should Be Equal 22 0xcafef010 285 Core Register Should Be Equal 23 0x89c9b54f 286 Core Register Should Be Equal 24 0x00000052 287 Core Register Should Be Equal 25 0x00000020 288 Core Register Should Be Equal 26 0x00000016 289 Core Register Should Be Equal 27 0x0000001a 290 Core Register Should Be Equal 28 0x00400000 291 Core Register Should Be Equal 29 0x00018000 292 Core Register Should Be Equal 30 0x00000000 293 Core Register Should Be Equal 31 0x00000804 294 295 Wide Register Should Be Equal 0 0x37adadaef9dbff5e738800755466a52c67a8c2216978ad1b257694340f09b7c8 296 Wide Register Should Be Equal 1 0x00000000000000000000000000000000baadf00dbaadf00dbaadf00dbaadf00d 297 Wide Register Should Be Equal 2 0x440659a832f54897440659a832f54898dd6208a5cc50f794dd6208a5cc50f791 298 Wide Register Should Be Equal 3 0x23a776b0bbc2837034745ffa22168ae87245a2d00357f208431165e5ed103473 299 Wide Register Should Be Equal 4 0xce52215b888f503cdf1f0aa4eee357b51cf04d7ad024bed4edbc1090b9dd0141 300 Wide Register Should Be Equal 5 0xfafeeeaebbb9f9dfabebbfef99fdf9dfefbafaaff9bfd9ffbaeebbbbdbff9bdb 301 Wide Register Should Be Equal 6 0x28a88802000889908888a00a88189108828aa820099818088822aa2a11109898 302 Wide Register Should Be Equal 7 0xd25666acbbb1704f23631fe511e568d76d30528ff027c1f732cc1191caef0343 303 Wide Register Should Be Equal 8 0x870333f9ddd7162976364ab077830eb1386507da9641a791679944c4ac896525 304 Wide Register Should Be Equal 9 0xd7c12b4df2c374c335d9da9bb4d6d555555554cccccccd55555554cccccccd55 305 Wide Register Should Be Equal 10 0x050111511112d2ed5414401032ced2ed1045054fd30cf2cd45114443f0cd30f0 306 Wide Register Should Be Equal 11 0xd75777fdccc4433c77775ff544b43bc47d7557dfc334b4c477dd55d5bbbc3433 307 Wide Register Should Be Equal 12 0x2caccd53332aa9a2ccccb54aab1aa22ad2caad35299b1b2acd32ab2b22229a9a 308 Wide Register Should Be Equal 13 0xa1a554085564a69a1252555a43c8b58a4a25a045a689a3aa2089656597ba66a7 309 Wide Register Should Be Equal 14 0x5ec45f47d09a8aecac10254c2c59e4068dba5ca7630e74e6bcee99917956327a 310 Wide Register Should Be Equal 15 0xdc58894eddd71629cb8ba00577830eb18dba5d2f9641a791bcee9a19ac896524 311 Wide Register Should Be Equal 16 0xce52215b888f503cdf1f0aa4eee357b51cf04d7ad024bed4edbc1090b9dd0141 312 Wide Register Should Be Equal 17 0x5555555533333333555555553333333355555555333333335555555533333331 313 Wide Register Should Be Equal 18 0x23a7769fbbc2838134745fe922168a4ec79af82569be586e9866bb3b53769ada 314 Wide Register Should Be Equal 19 0x28a88800000889828888a0098818910a828aa801099818000000000000000000 315 Wide Register Should Be Equal 20 0x78fccc062228e9d689c9b54f887cf14ec79af82569be57c3edbc10a1b9dd0130 316 Wide Register Should Be Equal 21 0x78fccc062228e9d689c9b54f887cf1eeefbafabdf9bfd9eebaeebbbbdbff9bfa 317 Wide Register Should Be Equal 22 0x78fccc062228e9d689c9b54f887cf1eeefbafabdf9bfd9eebaeebbbbdbff9db7 318 Wide Register Should Be Equal 23 0x78fccc062228e9d689c9b54f887cf1eeefbafabdf9bfd9eebaeebbbbdbff99f3 319 Wide Register Should Be Equal 24 0xccccccccbbbbbbbbaaaaaaaafacefeeddeadbeefcafed00dd0beb5331234abcd 320 Wide Register Should Be Equal 25 0xccccccccbbbbbbbbaaaaaaaafacefeeddeadbeefcafed00dd0beb5331234abcd 321 Wide Register Should Be Equal 26 0x78fccc062228e9d689c9b54f887cf1eeefbafabdf9bfd9eebaeebbbbdbff9bfa 322 Wide Register Should Be Equal 27 0x28a88802000889908888a00a88189108828aa820099818088822aa2a11109898 323 Wide Register Should Be Equal 28 0xd25666acbbb1704f23631fe511e568d76d30528ff027c1f732cc1191caef0343 324 Wide Register Should Be Equal 29 0x4f0d4b819f24f0c164341d3c26628bdb5763bcdf63388709e0654fefeb0953c2 325 Wide Register Should Be Equal 30 0x2167f87de9ee7ac7ffa3d88bab123192aee492924efa2ec9b55098e068ba2fa1 326 Wide Register Should Be Equal 31 0x37adadaef9dbff5e738800755466a52c67a8c2216978ad1b257694340f09b7c8 327 328
