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Searched refs:WREG32_SOC15 (Results 1 – 25 of 49) sorted by relevance

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/Linux-v5.10/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c298 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
300 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
302 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v1_0_mc_resume_spg_mode()
305 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
307 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
310 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v1_0_mc_resume_spg_mode()
314 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume_spg_mode()
317 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
319 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v1_0_mc_resume_spg_mode()
321 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v1_0_mc_resume_spg_mode()
[all …]
Dnavi10_ih.c76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in force_update_wptr_for_self_int()
81 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); in force_update_wptr_for_self_int()
103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_enable_interrupts()
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_enable_interrupts()
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_enable_interrupts()
160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_disable_interrupts()
164 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in navi10_ih_disable_interrupts()
165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in navi10_ih_disable_interrupts()
180 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_disable_interrupts()
[all …]
Dmmhub_v2_0.c182 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
184 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
187 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v2_0_init_gart_aperture_regs()
189 WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v2_0_init_gart_aperture_regs()
199 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0); in mmhub_v2_0_init_system_aperture_regs()
200 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, 0); in mmhub_v2_0_init_system_aperture_regs()
201 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, 0x00FFFFFF); in mmhub_v2_0_init_system_aperture_regs()
205 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v2_0_init_system_aperture_regs()
207 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v2_0_init_system_aperture_regs()
214 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_v2_0_init_system_aperture_regs()
[all …]
Dpsp_v3_1.c111 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sysdrv()
114 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sysdrv()
152 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v3_1_bootloader_load_sos()
155 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v3_1_bootloader_load_sos()
202 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); in psp_v3_1_reroute_ih()
203 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v3_1_reroute_ih()
204 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v3_1_reroute_ih()
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); in psp_v3_1_reroute_ih()
215 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v3_1_reroute_ih()
216 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v3_1_reroute_ih()
[all …]
Dvega10_ih.c59 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_enable_interrupts()
74 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_enable_interrupts()
90 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_enable_interrupts()
115 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in vega10_ih_disable_interrupts()
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in vega10_ih_disable_interrupts()
120 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in vega10_ih_disable_interrupts()
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in vega10_ih_disable_interrupts()
138 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); in vega10_ih_disable_interrupts()
139 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); in vega10_ih_disable_interrupts()
155 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in vega10_ih_disable_interrupts()
[all …]
Dgfxhub_v2_1.c140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_1_init_gart_aperture_regs()
147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_1_init_gart_aperture_regs()
156 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_1_init_system_aperture_regs()
157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_1_init_system_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); in gfxhub_v2_1_init_system_aperture_regs()
161 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v2_1_init_system_aperture_regs()
163 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v2_1_init_system_aperture_regs()
169 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v2_1_init_system_aperture_regs()
[all …]
Dgfxhub_v2_0.c140 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
142 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
145 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v2_0_init_gart_aperture_regs()
147 WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v2_0_init_gart_aperture_regs()
157 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0); in gfxhub_v2_0_init_system_aperture_regs()
158 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, 0); in gfxhub_v2_0_init_system_aperture_regs()
159 WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, 0x00FFFFFF); in gfxhub_v2_0_init_system_aperture_regs()
162 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
164 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in gfxhub_v2_0_init_system_aperture_regs()
170 WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v2_0_init_system_aperture_regs()
[all …]
Dpsp_v12_0.c147 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v12_0_bootloader_load_sysdrv()
150 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v12_0_bootloader_load_sysdrv()
188 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v12_0_bootloader_load_sos()
191 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v12_0_bootloader_load_sos()
213 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); in psp_v12_0_reroute_ih()
214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v12_0_reroute_ih()
215 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v12_0_reroute_ih()
225 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); in psp_v12_0_reroute_ih()
226 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v12_0_reroute_ih()
227 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); in psp_v12_0_reroute_ih()
[all …]
Dvcn_v2_0.c332 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
334 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
336 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
339 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
341 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
344 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_0_mc_resume()
348 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_0_mc_resume()
351 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
353 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
355 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_0_mc_resume()
[all …]
Dmmhub_v1_0.c74 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
76 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
79 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in mmhub_v1_0_init_gart_aperture_regs()
81 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in mmhub_v1_0_init_gart_aperture_regs()
91 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); in mmhub_v1_0_init_system_aperture_regs()
92 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); in mmhub_v1_0_init_system_aperture_regs()
93 WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); in mmhub_v1_0_init_system_aperture_regs()
96 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_v1_0_init_system_aperture_regs()
106 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v1_0_init_system_aperture_regs()
110 WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_v1_0_init_system_aperture_regs()
[all …]
Dpsp_v11_0.c254 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_kdb()
257 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_kdb()
287 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_spl()
290 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_spl()
320 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_sysdrv()
323 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_sysdrv()
356 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, in psp_v11_0_bootloader_load_sos()
359 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, in psp_v11_0_bootloader_load_sos()
381 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); in psp_v11_0_reroute_ih()
382 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); in psp_v11_0_reroute_ih()
[all …]
Dvcn_v2_5.c397 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
399 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
401 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
404 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
406 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
409 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
412 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
415 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
417 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
419 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
[all …]
Dvcn_v3_0.c432 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
434 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
436 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
439 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
441 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
444 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v3_0_mc_resume()
447 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v3_0_mc_resume()
450 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
452 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
454 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v3_0_mc_resume()
[all …]
Duvd_v7_0.c140 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
659 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
663 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
667 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in uvd_v7_0_mc_resume()
670 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
672 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in uvd_v7_0_mc_resume()
675 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, in uvd_v7_0_mc_resume()
679 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size); in uvd_v7_0_mc_resume()
[all …]
Dgfx_v9_4.c695 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
696 WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
697 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
698 WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
699 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
700 WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
702 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
703 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
704 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255); in gfx_v9_4_query_utc_edc_status()
705 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0); in gfx_v9_4_query_utc_edc_status()
[all …]
Dgfxhub_v1_0.c58 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
60 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
63 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, in gfxhub_v1_0_init_gart_aperture_regs()
65 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, in gfxhub_v1_0_init_gart_aperture_regs()
103 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in gfxhub_v1_0_init_system_aperture_regs()
105 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in gfxhub_v1_0_init_system_aperture_regs()
109 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, in gfxhub_v1_0_init_system_aperture_regs()
111 WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, in gfxhub_v1_0_init_system_aperture_regs()
188 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_0_enable_system_domain()
193 WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, in gfxhub_v1_0_disable_identity_aperture()
[all …]
Djpeg_v3_0.c228 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v3_0_disable_clock_gating()
236 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_disable_clock_gating()
243 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data); in jpeg_v3_0_disable_clock_gating()
256 WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data); in jpeg_v3_0_enable_clock_gating()
340 WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v3_0_start()
342 WREG32_SOC15(JPEG, 0, mmJPEG_ENC_GFX10_ADDR_CONFIG, in jpeg_v3_0_start()
354 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v3_0_start()
355 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v3_0_start()
356 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v3_0_start()
358 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v3_0_start()
[all …]
Dmes_v10_1.c422 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
425 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_enable()
432 WREG32_SOC15(GC, 0, mmCP_MES_DC_OP_CNTL, data); in mes_v10_1_enable()
436 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
444 WREG32_SOC15(GC, 0, mmCP_MES_CNTL, data); in mes_v10_1_enable()
469 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_CNTL, 0); in mes_v10_1_load_microcode()
476 WREG32_SOC15(GC, 0, mmCP_MES_PRGRM_CNTR_START, in mes_v10_1_load_microcode()
480 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_LO, in mes_v10_1_load_microcode()
482 WREG32_SOC15(GC, 0, mmCP_MES_IC_BASE_HI, in mes_v10_1_load_microcode()
486 WREG32_SOC15(GC, 0, mmCP_MES_MIBOUND_LO, 0x1FFFFF); in mes_v10_1_load_microcode()
[all …]
Dnbio_v7_0.c38 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, in nbio_v7_0_remap_hdp_registers()
40 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, in nbio_v7_0_remap_hdp_registers()
57 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v7_0_mc_access_enable()
60 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v7_0_mc_access_enable()
137 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v7_0_ih_doorbell_range()
144 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); in nbio_7_0_read_syshub_ind_mmr()
153 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset); in nbio_7_0_write_syshub_ind_mmr()
154 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data); in nbio_7_0_write_syshub_ind_mmr()
237 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v7_0_ih_control()
245 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v7_0_ih_control()
Dnbio_v7_4.c60 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, in nbio_v7_4_remap_hdp_registers()
62 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, in nbio_v7_4_remap_hdp_registers()
79 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v7_4_mc_access_enable()
82 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v7_4_mc_access_enable()
172 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v7_4_enable_doorbell_selfring_aperture()
174 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v7_4_enable_doorbell_selfring_aperture()
178 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp); in nbio_v7_4_enable_doorbell_selfring_aperture()
192 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v7_4_ih_doorbell_range()
243 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v7_4_ih_control()
251 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v7_4_ih_control()
[all …]
Dnbio_v2_3.c46 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL, in nbio_v2_3_remap_hdp_registers()
48 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL, in nbio_v2_3_remap_hdp_registers()
65 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v2_3_mc_access_enable()
69 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v2_3_mc_access_enable()
153 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v2_3_enable_doorbell_selfring_aperture()
155 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v2_3_enable_doorbell_selfring_aperture()
159 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL, in nbio_v2_3_enable_doorbell_selfring_aperture()
181 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v2_3_ih_doorbell_range()
189 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v2_3_ih_control()
203 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v2_3_ih_control()
Damdgpu_vcn.h71 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
72 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
84 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
126 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
136 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA, value); \
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
Djpeg_v2_5.c262 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
269 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_disable_clock_gating()
276 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data); in jpeg_v2_5_disable_clock_gating()
289 WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data); in jpeg_v2_5_enable_clock_gating()
317 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG, in jpeg_v2_5_start()
319 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG, in jpeg_v2_5_start()
331 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v2_5_start()
332 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L)); in jpeg_v2_5_start()
333 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v2_5_start()
335 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v2_5_start()
[all …]
Dnbio_v6_1.c46 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, in nbio_v6_1_mc_access_enable()
50 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0); in nbio_v6_1_mc_access_enable()
104 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW, in nbio_v6_1_enable_doorbell_selfring_aperture()
106 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH, in nbio_v6_1_enable_doorbell_selfring_aperture()
110 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp); in nbio_v6_1_enable_doorbell_selfring_aperture()
126 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range); in nbio_v6_1_ih_doorbell_range()
134 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8); in nbio_v6_1_ih_control()
142 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl); in nbio_v6_1_ih_control()
/Linux-v5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu9_smumgr.c98 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_101, msg); in smu9_send_msg_to_smc_without_waiting()
100 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); in smu9_send_msg_to_smc_without_waiting()
120 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); in smu9_send_msg_to_smc()
122 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc()
149 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_103, 0); in smu9_send_msg_to_smc_with_parameter()
150 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_102, parameter); in smu9_send_msg_to_smc_with_parameter()
152 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); in smu9_send_msg_to_smc_with_parameter()
153 WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); in smu9_send_msg_to_smc_with_parameter()

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