1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_atombios.h"
25 #include "nbio_v6_1.h"
26
27 #include "nbio/nbio_6_1_default.h"
28 #include "nbio/nbio_6_1_offset.h"
29 #include "nbio/nbio_6_1_sh_mask.h"
30 #include "nbio/nbio_6_1_smn.h"
31 #include "vega10_enum.h"
32
nbio_v6_1_get_rev_id(struct amdgpu_device * adev)33 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
34 {
35 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
36
37 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
38 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
39
40 return tmp;
41 }
42
nbio_v6_1_mc_access_enable(struct amdgpu_device * adev,bool enable)43 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
44 {
45 if (enable)
46 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
47 BIF_FB_EN__FB_READ_EN_MASK |
48 BIF_FB_EN__FB_WRITE_EN_MASK);
49 else
50 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
51 }
52
nbio_v6_1_hdp_flush(struct amdgpu_device * adev,struct amdgpu_ring * ring)53 static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
54 struct amdgpu_ring *ring)
55 {
56 if (!ring || !ring->funcs->emit_wreg)
57 WREG32_SOC15_NO_KIQ(NBIO, 0,
58 mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
59 0);
60 else
61 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
62 NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
63 }
64
nbio_v6_1_get_memsize(struct amdgpu_device * adev)65 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
66 {
67 return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
68 }
69
nbio_v6_1_sdma_doorbell_range(struct amdgpu_device * adev,int instance,bool use_doorbell,int doorbell_index,int doorbell_size)70 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
71 bool use_doorbell, int doorbell_index, int doorbell_size)
72 {
73 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
74 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
75
76 u32 doorbell_range = RREG32(reg);
77
78 if (use_doorbell) {
79 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
80 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
81 } else
82 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
83
84 WREG32(reg, doorbell_range);
85
86 }
87
nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device * adev,bool enable)88 static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
89 bool enable)
90 {
91 WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
92 }
93
nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device * adev,bool enable)94 static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
95 bool enable)
96 {
97 u32 tmp = 0;
98
99 if (enable) {
100 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
101 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
102 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
103
104 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
105 lower_32_bits(adev->doorbell.base));
106 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
107 upper_32_bits(adev->doorbell.base));
108 }
109
110 WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
111 }
112
113
nbio_v6_1_ih_doorbell_range(struct amdgpu_device * adev,bool use_doorbell,int doorbell_index)114 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
115 bool use_doorbell, int doorbell_index)
116 {
117 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
118
119 if (use_doorbell) {
120 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
121 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
122 BIF_IH_DOORBELL_RANGE, SIZE, 6);
123 } else
124 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
125
126 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
127 }
128
nbio_v6_1_ih_control(struct amdgpu_device * adev)129 static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
130 {
131 u32 interrupt_cntl;
132
133 /* setup interrupt control */
134 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
135 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
136 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
137 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
138 */
139 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
140 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
141 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
142 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
143 }
144
nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)145 static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
146 bool enable)
147 {
148 uint32_t def, data;
149
150 def = data = RREG32_PCIE(smnCPM_CONTROL);
151 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
152 data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
153 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
154 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
155 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
156 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
157 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
158 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
159 } else {
160 data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
161 CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
162 CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
163 CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
164 CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
165 CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
166 CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
167 }
168
169 if (def != data)
170 WREG32_PCIE(smnCPM_CONTROL, data);
171 }
172
nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)173 static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
174 bool enable)
175 {
176 uint32_t def, data;
177
178 def = data = RREG32_PCIE(smnPCIE_CNTL2);
179 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
180 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
181 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
182 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
183 } else {
184 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
185 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
186 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
187 }
188
189 if (def != data)
190 WREG32_PCIE(smnPCIE_CNTL2, data);
191 }
192
nbio_v6_1_get_clockgating_state(struct amdgpu_device * adev,u32 * flags)193 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
194 u32 *flags)
195 {
196 int data;
197
198 /* AMD_CG_SUPPORT_BIF_MGCG */
199 data = RREG32_PCIE(smnCPM_CONTROL);
200 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
201 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
202
203 /* AMD_CG_SUPPORT_BIF_LS */
204 data = RREG32_PCIE(smnPCIE_CNTL2);
205 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
206 *flags |= AMD_CG_SUPPORT_BIF_LS;
207 }
208
nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device * adev)209 static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
210 {
211 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
212 }
213
nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device * adev)214 static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
215 {
216 return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
217 }
218
nbio_v6_1_get_pcie_index_offset(struct amdgpu_device * adev)219 static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
220 {
221 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
222 }
223
nbio_v6_1_get_pcie_data_offset(struct amdgpu_device * adev)224 static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
225 {
226 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
227 }
228
229 const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
230 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
231 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
232 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
233 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
234 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
235 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
236 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
237 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
238 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
239 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
240 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
241 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
242 };
243
nbio_v6_1_init_registers(struct amdgpu_device * adev)244 static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
245 {
246 uint32_t def, data;
247
248 def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
249 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
250 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
251
252 if (def != data)
253 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
254
255 def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
256 data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
257
258 if (def != data)
259 WREG32_PCIE(smnPCIE_CI_CNTL, data);
260 }
261
262 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
263 .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
264 .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
265 .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
266 .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
267 .get_rev_id = nbio_v6_1_get_rev_id,
268 .mc_access_enable = nbio_v6_1_mc_access_enable,
269 .hdp_flush = nbio_v6_1_hdp_flush,
270 .get_memsize = nbio_v6_1_get_memsize,
271 .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
272 .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
273 .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
274 .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
275 .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
276 .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
277 .get_clockgating_state = nbio_v6_1_get_clockgating_state,
278 .ih_control = nbio_v6_1_ih_control,
279 .init_registers = nbio_v6_1_init_registers,
280 };
281
