Lines Matching refs:WREG32_SOC15
76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in force_update_wptr_for_self_int()
80 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in force_update_wptr_for_self_int()
81 WREG32_SOC15(OSSSYS, 0, mmIH_CNTL2, ih_cntl); in force_update_wptr_for_self_int()
103 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_enable_interrupts()
119 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_enable_interrupts()
135 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_enable_interrupts()
160 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_disable_interrupts()
164 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in navi10_ih_disable_interrupts()
165 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in navi10_ih_disable_interrupts()
180 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_disable_interrupts()
183 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); in navi10_ih_disable_interrupts()
184 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); in navi10_ih_disable_interrupts()
200 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_disable_interrupts()
203 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); in navi10_ih_disable_interrupts()
204 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); in navi10_ih_disable_interrupts()
258 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12); in navi10_ih_reroute_ih()
262 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); in navi10_ih_reroute_ih()
265 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B); in navi10_ih_reroute_ih()
268 WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp); in navi10_ih_reroute_ih()
294 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8); in navi10_ih_irq_init()
295 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff); in navi10_ih_irq_init()
307 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); in navi10_ih_irq_init()
320 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid, ih_chicken); in navi10_ih_irq_init()
326 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken); in navi10_ih_irq_init()
333 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, in navi10_ih_irq_init()
335 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, in navi10_ih_irq_init()
339 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0); in navi10_ih_irq_init()
340 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0); in navi10_ih_irq_init()
342 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR, in navi10_ih_irq_init()
350 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8); in navi10_ih_irq_init()
351 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1, in navi10_ih_irq_init()
367 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl); in navi10_ih_irq_init()
370 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0); in navi10_ih_irq_init()
371 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0); in navi10_ih_irq_init()
373 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1, in navi10_ih_irq_init()
379 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8); in navi10_ih_irq_init()
380 WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2, in navi10_ih_irq_init()
393 WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl); in navi10_ih_irq_init()
396 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0); in navi10_ih_irq_init()
397 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0); in navi10_ih_irq_init()
399 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2, in navi10_ih_irq_init()
407 WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp); in navi10_ih_irq_init()
411 WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp); in navi10_ih_irq_init()
592 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); in navi10_ih_set_rptr()
594 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr); in navi10_ih_set_rptr()
596 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr); in navi10_ih_set_rptr()
782 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data); in navi10_ih_update_clockgating_state()