59 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);  in vega10_ih_enable_interrupts()
74 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);  in vega10_ih_enable_interrupts()
90 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);  in vega10_ih_enable_interrupts()
115 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);  in vega10_ih_disable_interrupts()
119 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);  in vega10_ih_disable_interrupts()
120 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);  in vega10_ih_disable_interrupts()
135 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);  in vega10_ih_disable_interrupts()
138 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);  in vega10_ih_disable_interrupts()
139 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);  in vega10_ih_disable_interrupts()
155 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);  in vega10_ih_disable_interrupts()
159 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);  in vega10_ih_disable_interrupts()
160 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);  in vega10_ih_disable_interrupts()
233 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE, ih->gpu_addr >> 8);  in vega10_ih_irq_init()
234 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI, (ih->gpu_addr >> 40) & 0xff);  in vega10_ih_irq_init()
246 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);  in vega10_ih_irq_init()
260 		WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);  in vega10_ih_irq_init()
264 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO,  in vega10_ih_irq_init()
266 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI,  in vega10_ih_irq_init()
270 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);  in vega10_ih_irq_init()
271 	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);  in vega10_ih_irq_init()
273 	WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR,  in vega10_ih_irq_init()
278 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING1, ih->gpu_addr >> 8);  in vega10_ih_irq_init()
279 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING1,  in vega10_ih_irq_init()
295 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);  in vega10_ih_irq_init()
299 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING1, 0);  in vega10_ih_irq_init()
300 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, 0);  in vega10_ih_irq_init()
302 		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1,  in vega10_ih_irq_init()
308 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_RING2, ih->gpu_addr >> 8);  in vega10_ih_irq_init()
309 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_BASE_HI_RING2,  in vega10_ih_irq_init()
322 			WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING2, ih_rb_cntl);  in vega10_ih_irq_init()
326 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_RING2, 0);  in vega10_ih_irq_init()
327 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, 0);  in vega10_ih_irq_init()
329 		WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2,  in vega10_ih_irq_init()
336 	WREG32_SOC15(OSSSYS, 0, mmIH_STORM_CLIENT_LIST_CNTL, tmp);  in vega10_ih_irq_init()
340 	WREG32_SOC15(OSSSYS, 0, mmIH_INT_FLOOD_CNTL, tmp);  in vega10_ih_irq_init()
522 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr);  in vega10_ih_set_rptr()
524 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING1, ih->rptr);  in vega10_ih_set_rptr()
526 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR_RING2, ih->rptr);  in vega10_ih_set_rptr()
710 			WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);  in vega10_ih_update_clockgating_state()