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/Linux-v5.15/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv50.c34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src() local
60 switch (device->chipset) { in read_pll_src()
73 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); in read_pll_src()
74 ref *= (coef & 0x01000000) ? 2 : 4; in read_pll_src()
75 P = (coef & 0x00070000) >> 16; in read_pll_src()
76 N = ((coef & 0x0000ff00) >> 8) + 1; in read_pll_src()
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Dnv40.c42 struct nvkm_device *device = clk->base.subdev.device; in read_pll_1()
58 struct nvkm_device *device = clk->base.subdev.device; in read_pll_2()
60 u32 coef = nvkm_rd32(device, reg + 0x04); in read_pll_2() local
61 int N2 = (coef & 0xff000000) >> 24; in read_pll_2()
62 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2()
63 int N1 = (coef & 0x0000ff00) >> 8; in read_pll_2()
64 int M1 = (coef & 0x000000ff) >> 0; in read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src) in read_clk() argument
84 switch (src) { in read_clk()
97 nv40_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in nv40_clk_read() argument
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Dgf100.c38 u32 coef; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
63 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
64 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
65 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
66 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
75 sclk = device->crystal; in read_pll()
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Dgk104.c38 u32 coef; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
64 u32 coef = nvkm_rd32(device, pll + 0x04); in read_pll() local
65 u32 P = (coef & 0x003f0000) >> 16; in read_pll()
66 u32 N = (coef & 0x0000ff00) >> 8; in read_pll()
67 u32 M = (coef & 0x000000ff) >> 0; in read_pll()
77 sclk = device->crystal; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
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Dgt215.c45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
117 u32 coef = nvkm_rd32(device, pll + 4); in read_pll() local
118 M = (coef & 0x000000ff) >> 0; in read_pll()
119 N = (coef & 0x0000ff00) >> 8; in read_pll()
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Dmcp77.c44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
53 u32 coef = nvkm_rd32(device, base + 4); in read_pll() local
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
71 M1 = (coef & 0x000000ff); in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
89 switch (src) { in mcp77_clk_read()
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/Linux-v5.15/drivers/media/platform/sti/bdisp/
Dbdisp-hw.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "bdisp-filter.h"
11 #include "bdisp-reg.h"
27 bool cconv; /* RGB - YUV conversion */
34 bool src_interlaced; /* is the src an interlaced buffer */
35 u8 src_nbp; /* nb of planes of the src */
36 bool src_yuv; /* is the src a YUV color format */
37 bool src_420; /* is the src 4:2:0 chroma subsampled */
54 .coef = {
68 .coef = {
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/Linux-v5.15/drivers/dma/ioat/
Dprep.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright(c) 2004 - 2015 Intel Corporation.
10 #include <linux/dma-mapping.h>
36 raw->field[xor_idx_to_field[idx]] = addr + offset; in xor_set_src()
43 return raw->field[pq_idx_to_field[idx]]; in pq_get_src()
50 return raw->field[pq16_idx_to_field[idx]]; in pq16_get_src()
54 dma_addr_t addr, u32 offset, u8 coef, int idx) in pq_set_src() argument
59 raw->field[pq_idx_to_field[idx]] = addr + offset; in pq_set_src()
60 pq->coef[idx] = coef; in pq_set_src()
64 dma_addr_t addr, u32 offset, u8 coef, unsigned idx) in pq16_set_src() argument
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/Linux-v5.15/crypto/async_tx/
Dasync_raid6_recov.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Asynchronous RAID-6 recovery calculations ASYNC_TX API.
12 #include <linux/dma-mapping.h>
19 struct page **srcs, unsigned int *src_offs, unsigned char *coef, in async_sum_product() argument
24 struct dma_device *dma = chan ? chan->device : NULL; in async_sum_product()
31 unmap = dmaengine_get_unmap_data(dma->dev, 3, GFP_NOWAIT); in async_sum_product()
34 struct device *dev = dma->dev; in async_sum_product()
39 if (submit->flags & ASYNC_TX_FENCE) in async_sum_product()
41 unmap->addr[0] = dma_map_page(dev, srcs[0], src_offs[0], in async_sum_product()
43 unmap->addr[1] = dma_map_page(dev, srcs[1], src_offs[1], in async_sum_product()
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/Linux-v5.15/include/linux/mfd/
Dac100.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
91 #define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */
92 #define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */
93 #define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */
94 #define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */
100 #define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */
101 #define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */
102 #define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */
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/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
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Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller Device Tree Bindings
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy@[0-9a-f]+$"
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/Linux-v5.15/sound/pci/hda/
Dpatch_cirrus.c1 // SPDX-License-Identifier: GPL-2.0-or-later
66 /* Vendor-specific processing widget */
73 /* coef indices */
79 * 1 = digital immediate, analog zero-cross
80 * 2 = digtail & analog soft-ramp
81 * 3 = digital soft-ramp, analog zero-cross
85 #define CS_COEF_ADC_LI_SZC_MODE (3 << 0) /* SZC setup for line-in */
86 /* PGA mode: 0 = differential, 1 = signle-ended */
88 #define CS_COEF_ADC_LI_PGA_MODE (1 << 6) /* PGA setup for line-in */
92 * 1 = zero-cross
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/Linux-v5.15/drivers/dma/
Dfsl_raid.c13 * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
66 #include <linux/dma-mapping.h>
85 /* Add descriptors into per chan software queue - submit_q */
94 re_chan = container_of(tx->chan, struct fsl_re_chan, chan); in fsl_re_tx_submit()
96 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
98 list_add_tail(&desc->node, &re_chan->submit_q); in fsl_re_tx_submit()
99 spin_unlock_irqrestore(&re_chan->desc_lock, flags); in fsl_re_tx_submit()
114 spin_lock_irqsave(&re_chan->desc_lock, flags); in fsl_re_issue_pending()
116 in_be32(&re_chan->jrregs->inbring_slot_avail)); in fsl_re_issue_pending()
118 list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) { in fsl_re_issue_pending()
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Diop-adma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/platform_data/dma-iop32x.h>
12 #define DMA_CCR(chan) (chan->mmr_base + 0x0)
13 #define DMA_CSR(chan) (chan->mmr_base + 0x4)
14 #define DMA_DAR(chan) (chan->mmr_base + 0xc)
15 #define DMA_NDAR(chan) (chan->mmr_base + 0x10)
16 #define DMA_PADR(chan) (chan->mmr_base + 0x14)
17 #define DMA_PUADR(chan) (chan->mmr_base + 0x18)
18 #define DMA_LADR(chan) (chan->mmr_base + 0x1c)
19 #define DMA_BCR(chan) (chan->mmr_base + 0x20)
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/Linux-v5.15/drivers/gpu/drm/sti/
Dsti_hqvdp.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/dma-mapping.h>
29 #define HQVDP_FMW_NAME "hqvdp-stih407.bin"
374 * -1 in error cases
379 u32 cmd = hqvdp->hqvdp_cmd_paddr; in sti_hqvdp_get_free_cmd()
382 curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD); in sti_hqvdp_get_free_cmd()
383 next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD); in sti_hqvdp_get_free_cmd()
391 return -1; in sti_hqvdp_get_free_cmd()
402 * -1 in error cases
407 u32 cmd = hqvdp->hqvdp_cmd_paddr; in sti_hqvdp_get_curr_cmd()
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/Linux-v5.15/drivers/phy/mediatek/
Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
119 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
125 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
168 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
175 dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in u2_phy_slew_rate_calibrate()
176 inst->index, fm_out, calib_val, in u2_phy_slew_rate_calibrate()
177 xsphy->src_ref_clk, xsphy->src_coef); in u2_phy_slew_rate_calibrate()
194 void __iomem *pbase = inst->port_base; in u2_phy_instance_init()
210 void __iomem *pbase = inst->port_base; in u2_phy_instance_power_on()
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Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
21 /* version V1 sub-banks offset base address */
32 /* version V2/V3 sub-banks offset base address */
228 /* CDR Charge Pump P-path current adjustment */
254 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
266 /* I-path capacitance adjustment for Gen1 */
360 struct u2phy_banks *u2_banks = &instance->u2_banks; in hs_slew_rate_calibrate()
361 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate()
362 void __iomem *com = u2_banks->com; in hs_slew_rate_calibrate()
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/Linux-v5.15/drivers/gpu/drm/tidss/
Dtidss_dispc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/dma-mapping.h>
78 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
81 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
154 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
157 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
243 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
246 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
312 iowrite32(val, dispc->base_common + reg); in dispc_write()
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/Linux-v5.15/sound/pci/nm256/
Dnm256.c1 // SPDX-License-Identifier: GPL-2.0-or-later
178 u32 buf; /* offset from chip->buffer */
209 unsigned int use_cache: 1; /* use one big coef. table */
264 return readb(chip->cport + offset); in snd_nm256_readb()
270 return readw(chip->cport + offset); in snd_nm256_readw()
276 return readl(chip->cport + offset); in snd_nm256_readl()
282 writeb(val, chip->cport + offset); in snd_nm256_writeb()
288 writew(val, chip->cport + offset); in snd_nm256_writew()
294 writel(val, chip->cport + offset); in snd_nm256_writel()
298 snd_nm256_write_buffer(struct nm256 *chip, const void *src, int offset, int size) in snd_nm256_write_buffer() argument
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/Linux-v5.15/drivers/dma/ppc4xx/
Dadma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2009 DENX Software Engineering.
22 #include <linux/dma-mapping.h>
33 #include <asm/dcr-regs.h>
91 /* This array is used in data-check operations for storing a pattern */
98 /* Since RXOR operations use the common register (MQ0_CF2H) for setting-up
135 switch (chan->device->id) { in print_cb()
145 cdb, chan->device->id, in print_cb()
146 cdb->attr, cdb->opc, le32_to_cpu(cdb->cnt), in print_cb()
147 le32_to_cpu(cdb->sg1u), le32_to_cpu(cdb->sg1l), in print_cb()
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/Linux-v5.15/drivers/staging/media/atomisp/pci/runtime/debug/src/
Dia_css_debug.c1 // SPDX-License-Identifier: GPL-2.0
190 fw->info.sp.threads_stack, in debug_dump_sp_stack_info()
191 fw->info.sp.threads_stack_size); in debug_dump_sp_stack_info()
193 HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack; in debug_dump_sp_stack_info()
194 HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size; in debug_dump_sp_stack_info()
196 if (fw->info.sp.threads_stack == 0 || in debug_dump_sp_stack_info()
197 fw->info.sp.threads_stack_size == 0) in debug_dump_sp_stack_info()
240 return "yuv420-8-legacy"; in debug_stream_format2str()
242 return "yuv420-8"; in debug_stream_format2str()
244 return "yuv420-10"; in debug_stream_format2str()
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/Linux-v5.15/drivers/net/wireless/ath/ath9k/
Dar9003_phy.c2 * Copyright (c) 2010-2011 Atheros Communications Inc.
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
129 * This is the function to change channel on single-chip devices, that is
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
187 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
223 ah->curchan = chan; in ar9003_hw_set_channel()
229 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
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/Linux-v5.15/drivers/staging/media/atomisp/pci/
Datomisp_cmd.c1 // SPDX-License-Identifier: GPL-2.0
32 #include <media/v4l2-event.h>
33 #include <media/videobuf-vmalloc.h>
43 #include "atomisp-regs.h"
85 * get sensor:dis71430/ov2720 related info from v4l2_subdev->priv data field.
86 * subdev->priv is set in mrst.c
114 struct atomisp_device *isp = asd->isp; in atomisp_get_sensor_fps()
119 ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, in atomisp_get_sensor_fps()
132 * 2. Ratio is calculated using formula: 2 * HPLL / target frequency - 1
136 * 4. Wait for FREQVALID to be cleared by P-Unit.
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