1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
21 /* version V1 sub-banks offset base address */
32 /* version V2/V3 sub-banks offset base address */
228 /* CDR Charge Pump P-path current adjustment */
254 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
266 /* I-path capacitance adjustment for Gen1 */
360 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in hs_slew_rate_calibrate()
361 	void __iomem *fmreg = u2_banks->fmreg;  in hs_slew_rate_calibrate()
362 	void __iomem *com = u2_banks->com;  in hs_slew_rate_calibrate()
368 	if (tphy->pdata->version == MTK_PHY_V3)  in hs_slew_rate_calibrate()
372 	if (instance->eye_src)  in hs_slew_rate_calibrate()
390 	if (tphy->pdata->version == MTK_PHY_V1)  in hs_slew_rate_calibrate()
391 		tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);  in hs_slew_rate_calibrate()
417 		/* ( 1024 / FM_OUT ) x reference clock frequency x coef */  in hs_slew_rate_calibrate()
418 		tmp = tphy->src_ref_clk * tphy->src_coef;  in hs_slew_rate_calibrate()
425 	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in hs_slew_rate_calibrate()
426 		instance->index, fm_out, calibration_val,  in hs_slew_rate_calibrate()
427 		tphy->src_ref_clk, tphy->src_coef);  in hs_slew_rate_calibrate()
444 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in u3_phy_instance_init()
448 	tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);  in u3_phy_instance_init()
450 	writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);  in u3_phy_instance_init()
453 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);  in u3_phy_instance_init()
456 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);  in u3_phy_instance_init()
458 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);  in u3_phy_instance_init()
461 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);  in u3_phy_instance_init()
463 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);  in u3_phy_instance_init()
466 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);  in u3_phy_instance_init()
468 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);  in u3_phy_instance_init()
471 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);  in u3_phy_instance_init()
473 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);  in u3_phy_instance_init()
476 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);  in u3_phy_instance_init()
478 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);  in u3_phy_instance_init()
481 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);  in u3_phy_instance_init()
483 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);  in u3_phy_instance_init()
486 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);  in u3_phy_instance_init()
488 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in u3_phy_instance_init()
494 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_pll_26m_set()
495 	void __iomem *com = u2_banks->com;  in u2_phy_pll_26m_set()
498 	if (!tphy->pdata->sw_pll_48m_to_26m)  in u2_phy_pll_26m_set()
521 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_init()
522 	void __iomem *com = u2_banks->com;  in u2_phy_instance_init()
523 	u32 index = instance->index;  in u2_phy_instance_init()
551 	if (tphy->pdata->avoid_rx_sen_degradation) {  in u2_phy_instance_init()
580 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_init()
586 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_on()
587 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_on()
588 	u32 index = instance->index;  in u2_phy_instance_power_on()
605 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_on()
614 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
620 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_power_off()
621 	void __iomem *com = u2_banks->com;  in u2_phy_instance_power_off()
622 	u32 index = instance->index;  in u2_phy_instance_power_off()
639 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_power_off()
649 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
655 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_exit()
656 	void __iomem *com = u2_banks->com;  in u2_phy_instance_exit()
657 	u32 index = instance->index;  in u2_phy_instance_exit()
660 	if (tphy->pdata->avoid_rx_sen_degradation && index) {  in u2_phy_instance_exit()
675 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_instance_set_mode()
678 	tmp = readl(u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
693 	writel(tmp, u2_banks->com + U3P_U2PHYDTM1);  in u2_phy_instance_set_mode()
699 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in pcie_phy_instance_init()
702 	if (tphy->pdata->version != MTK_PHY_V1)  in pcie_phy_instance_init()
705 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);  in pcie_phy_instance_init()
708 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);  in pcie_phy_instance_init()
711 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);  in pcie_phy_instance_init()
714 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);  in pcie_phy_instance_init()
716 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);  in pcie_phy_instance_init()
719 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);  in pcie_phy_instance_init()
721 	/* SSC delta -5000ppm */  in pcie_phy_instance_init()
722 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);  in pcie_phy_instance_init()
725 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);  in pcie_phy_instance_init()
727 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);  in pcie_phy_instance_init()
730 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);  in pcie_phy_instance_init()
733 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);  in pcie_phy_instance_init()
736 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);  in pcie_phy_instance_init()
738 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);  in pcie_phy_instance_init()
741 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);  in pcie_phy_instance_init()
743 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);  in pcie_phy_instance_init()
746 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);  in pcie_phy_instance_init()
748 	tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);  in pcie_phy_instance_init()
751 	writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);  in pcie_phy_instance_init()
753 	/* Tx Detect Rx Timing: 10us -> 5us */  in pcie_phy_instance_init()
754 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);  in pcie_phy_instance_init()
757 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);  in pcie_phy_instance_init()
759 	tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);  in pcie_phy_instance_init()
762 	writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);  in pcie_phy_instance_init()
766 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in pcie_phy_instance_init()
772 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_on()
775 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);  in pcie_phy_instance_power_on()
777 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);  in pcie_phy_instance_power_on()
779 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);  in pcie_phy_instance_power_on()
781 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);  in pcie_phy_instance_power_on()
788 	struct u3phy_banks *bank = &instance->u3_banks;  in pcie_phy_instance_power_off()
791 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);  in pcie_phy_instance_power_off()
793 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);  in pcie_phy_instance_power_off()
795 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);  in pcie_phy_instance_power_off()
797 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);  in pcie_phy_instance_power_off()
803 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in sata_phy_instance_init()
804 	void __iomem *phyd = u3_banks->phyd;  in sata_phy_instance_init()
855 	dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);  in sata_phy_instance_init()
861 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v1_banks_init()
862 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v1_banks_init()
864 	switch (instance->type) {  in phy_v1_banks_init()
866 		u2_banks->misc = NULL;  in phy_v1_banks_init()
867 		u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;  in phy_v1_banks_init()
868 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;  in phy_v1_banks_init()
872 		u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;  in phy_v1_banks_init()
873 		u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;  in phy_v1_banks_init()
874 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
875 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;  in phy_v1_banks_init()
878 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;  in phy_v1_banks_init()
881 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v1_banks_init()
889 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in phy_v2_banks_init()
890 	struct u3phy_banks *u3_banks = &instance->u3_banks;  in phy_v2_banks_init()
892 	switch (instance->type) {  in phy_v2_banks_init()
894 		u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;  in phy_v2_banks_init()
895 		u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;  in phy_v2_banks_init()
896 		u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;  in phy_v2_banks_init()
900 		u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;  in phy_v2_banks_init()
901 		u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;  in phy_v2_banks_init()
902 		u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;  in phy_v2_banks_init()
903 		u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;  in phy_v2_banks_init()
906 		dev_err(tphy->dev, "incompatible PHY type\n");  in phy_v2_banks_init()
914 	struct device *dev = &instance->phy->dev;  in phy_parse_property()
916 	if (instance->type != PHY_TYPE_USB2)  in phy_parse_property()
919 	instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12");  in phy_parse_property()
920 	device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
921 				 &instance->eye_src);  in phy_parse_property()
922 	device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
923 				 &instance->eye_vrt);  in phy_parse_property()
924 	device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
925 				 &instance->eye_term);  in phy_parse_property()
927 				 &instance->intr);  in phy_parse_property()
929 				 &instance->discth);  in phy_parse_property()
930 	dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n",  in phy_parse_property()
931 		instance->bc12_en, instance->eye_src,  in phy_parse_property()
932 		instance->eye_vrt, instance->eye_term,  in phy_parse_property()
933 		instance->intr, instance->discth);  in phy_parse_property()
939 	struct u2phy_banks *u2_banks = &instance->u2_banks;  in u2_phy_props_set()
940 	void __iomem *com = u2_banks->com;  in u2_phy_props_set()
943 	if (instance->bc12_en) {  in u2_phy_props_set()
949 	if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) {  in u2_phy_props_set()
952 		tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);  in u2_phy_props_set()
956 	if (instance->eye_vrt) {  in u2_phy_props_set()
959 		tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);  in u2_phy_props_set()
963 	if (instance->eye_term) {  in u2_phy_props_set()
966 		tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);  in u2_phy_props_set()
970 	if (instance->intr) {  in u2_phy_props_set()
973 		tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);  in u2_phy_props_set()
977 	if (instance->discth) {  in u2_phy_props_set()
980 		tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);  in u2_phy_props_set()
993 	if (!of_property_read_bool(dn, "mediatek,syscon-type"))  in phy_type_syscon_get()
996 	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",  in phy_type_syscon_get()
1001 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
1002 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
1003 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
1005 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
1006 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
1008 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
1016 	if (!instance->type_sw)  in phy_type_set()
1019 	switch (instance->type) {  in phy_type_set()
1037 	mask = RG_PHY_SW_TYPE << (instance->type_sw_index * BITS_PER_BYTE);  in phy_type_set()
1038 	regmap_update_bits(instance->type_sw, instance->type_sw_reg, mask, type);  in phy_type_set()
1046 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
1049 	ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1053 	switch (instance->type) {  in mtk_phy_init()
1071 		dev_err(tphy->dev, "incompatible PHY type\n");  in mtk_phy_init()
1072 		clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_init()
1073 		return -EINVAL;  in mtk_phy_init()
1082 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
1084 	if (instance->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
1087 	} else if (instance->type == PHY_TYPE_PCIE) {  in mtk_phy_power_on()
1097 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
1099 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
1101 	else if (instance->type == PHY_TYPE_PCIE)  in mtk_phy_power_off()
1110 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_exit()
1112 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_exit()
1115 	clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks);  in mtk_phy_exit()
1122 	struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
1124 	if (instance->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
1135 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
1138 	if (args->args_count != 1) {  in mtk_phy_xlate()
1140 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1143 	for (index = 0; index < tphy->nphys; index++)  in mtk_phy_xlate()
1144 		if (phy_np == tphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
1145 			instance = tphy->phys[index];  in mtk_phy_xlate()
1151 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1154 	instance->type = args->args[0];  in mtk_phy_xlate()
1155 	if (!(instance->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
1156 	      instance->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
1157 	      instance->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
1158 	      instance->type == PHY_TYPE_SATA ||  in mtk_phy_xlate()
1159 	      instance->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
1160 		dev_err(dev, "unsupported device type: %d\n", instance->type);  in mtk_phy_xlate()
1161 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1164 	switch (tphy->pdata->version) {  in mtk_phy_xlate()
1174 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
1180 	return instance->phy;  in mtk_phy_xlate()
1217 	{ .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1218 	{ .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1219 	{ .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1220 	{ .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata },
1221 	{ .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1222 	{ .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1223 	{ .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata },
1230 	struct device *dev = &pdev->dev;  in mtk_tphy_probe()
1231 	struct device_node *np = dev->of_node;  in mtk_tphy_probe()
1241 		return -ENOMEM;  in mtk_tphy_probe()
1243 	tphy->pdata = of_device_get_match_data(dev);  in mtk_tphy_probe()
1244 	if (!tphy->pdata)  in mtk_tphy_probe()
1245 		return -EINVAL;  in mtk_tphy_probe()
1247 	tphy->nphys = of_get_child_count(np);  in mtk_tphy_probe()
1248 	tphy->phys = devm_kcalloc(dev, tphy->nphys,  in mtk_tphy_probe()
1249 				       sizeof(*tphy->phys), GFP_KERNEL);  in mtk_tphy_probe()
1250 	if (!tphy->phys)  in mtk_tphy_probe()
1251 		return -ENOMEM;  in mtk_tphy_probe()
1253 	tphy->dev = dev;  in mtk_tphy_probe()
1258 	if (sif_res && tphy->pdata->version == MTK_PHY_V1) {  in mtk_tphy_probe()
1260 		tphy->sif_base = devm_ioremap_resource(dev, sif_res);  in mtk_tphy_probe()
1261 		if (IS_ERR(tphy->sif_base)) {  in mtk_tphy_probe()
1263 			return PTR_ERR(tphy->sif_base);  in mtk_tphy_probe()
1267 	if (tphy->pdata->version < MTK_PHY_V3) {  in mtk_tphy_probe()
1268 		tphy->src_ref_clk = U3P_REF_CLK;  in mtk_tphy_probe()
1269 		tphy->src_coef = U3P_SLEW_RATE_COEF;  in mtk_tphy_probe()
1271 		device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",  in mtk_tphy_probe()
1272 					 &tphy->src_ref_clk);  in mtk_tphy_probe()
1273 		device_property_read_u32(dev, "mediatek,src-coef",  in mtk_tphy_probe()
1274 					 &tphy->src_coef);  in mtk_tphy_probe()
1286 			retval = -ENOMEM;  in mtk_tphy_probe()
1290 		tphy->phys[port] = instance;  in mtk_tphy_probe()
1299 		subdev = &phy->dev;  in mtk_tphy_probe()
1302 			dev_err(subdev, "failed to get address resource(id-%d)\n",  in mtk_tphy_probe()
1307 		instance->port_base = devm_ioremap_resource(subdev, &res);  in mtk_tphy_probe()
1308 		if (IS_ERR(instance->port_base)) {  in mtk_tphy_probe()
1309 			retval = PTR_ERR(instance->port_base);  in mtk_tphy_probe()
1313 		instance->phy = phy;  in mtk_tphy_probe()
1314 		instance->index = port;  in mtk_tphy_probe()
1318 		clks = instance->clks;  in mtk_tphy_probe()
1341 		.name	= "mtk-tphy",
1349 MODULE_DESCRIPTION("MediaTek T-PHY driver");