1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/platform_data/dma-iop32x.h>
12 #define DMA_CCR(chan)		(chan->mmr_base + 0x0)
13 #define DMA_CSR(chan)		(chan->mmr_base + 0x4)
14 #define DMA_DAR(chan)		(chan->mmr_base + 0xc)
15 #define DMA_NDAR(chan)		(chan->mmr_base + 0x10)
16 #define DMA_PADR(chan)		(chan->mmr_base + 0x14)
17 #define DMA_PUADR(chan)	(chan->mmr_base + 0x18)
18 #define DMA_LADR(chan)		(chan->mmr_base + 0x1c)
19 #define DMA_BCR(chan)		(chan->mmr_base + 0x20)
20 #define DMA_DCR(chan)		(chan->mmr_base + 0x24)
23 #define AAU_ACR(chan)		(chan->mmr_base + 0x0)
24 #define AAU_ASR(chan)		(chan->mmr_base + 0x4)
25 #define AAU_ADAR(chan)		(chan->mmr_base + 0x8)
26 #define AAU_ANDAR(chan)	(chan->mmr_base + 0xc)
27 #define AAU_SAR(src, chan)	(chan->mmr_base + (0x10 + ((src) << 2)))  argument
28 #define AAU_DAR(chan)		(chan->mmr_base + 0x20)
29 #define AAU_ABCR(chan)		(chan->mmr_base + 0x24)
30 #define AAU_ADCR(chan)		(chan->mmr_base + 0x28)
31 #define AAU_SAR_EDCR(src_edc)	(chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
105 	u32 src[4];  member
128 	u32 src[3];  member
195 			 dma_addr_t addr, unsigned char coef)  in iop_desc_set_pq_src_addr()  argument
224 			      dma_addr_t *src)  in iop_desc_set_pq_zero_sum_addr()  argument
242 	int id = chan->device->id;  in iop_chan_get_current_descriptor()
259 	int id = chan->device->id;  in iop_chan_set_next_descriptor()
288 	return (desc->idx & (num_slots - 1)) ? 0 : 1;  in iop_desc_is_aligned()
309 						1, 1, 1, 1, /* 01 - 04 */  in iop3xx_aau_xor_slot_count()
310 						2, 2, 2, 2, /* 05 - 08 */  in iop3xx_aau_xor_slot_count()
311 						4, 4, 4, 4, /* 09 - 12 */  in iop3xx_aau_xor_slot_count()
312 						4, 4, 4, 4, /* 13 - 16 */  in iop3xx_aau_xor_slot_count()
313 						8, 8, 8, 8, /* 17 - 20 */  in iop3xx_aau_xor_slot_count()
314 						8, 8, 8, 8, /* 21 - 24 */  in iop3xx_aau_xor_slot_count()
315 						8, 8, 8, 8, /* 25 - 28 */  in iop3xx_aau_xor_slot_count()
316 						8, 8, 8, 8, /* 29 - 32 */  in iop3xx_aau_xor_slot_count()
318 	*slots_per_op = slot_count_table[src_cnt - 1];  in iop3xx_aau_xor_slot_count()
325 	switch (chan->device->id) {  in iop_chan_interrupt_slot_count()
345 	len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;  in iop_chan_xor_slot_count()
347 		len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;  in iop_chan_xor_slot_count()
367 	len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;  in iop_chan_zero_sum_slot_count()
369 		len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;  in iop_chan_zero_sum_slot_count()
381 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_get_byte_count()
383 	switch (chan->device->id) {  in iop_desc_get_byte_count()
386 		return hw_desc.dma->byte_count;  in iop_desc_get_byte_count()
388 		return hw_desc.aau->byte_count;  in iop_desc_get_byte_count()
415 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_get_src_addr()
417 	switch (chan->device->id) {  in iop_desc_get_src_addr()
420 		return hw_desc.dma->src_addr;  in iop_desc_get_src_addr()
428 		return hw_desc.aau->src[src_idx];  in iop_desc_get_src_addr()
430 		return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;  in iop_desc_get_src_addr()
437 		hw_desc->src[src_idx] = addr;  in iop3xx_aau_desc_set_src_addr()
439 		hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;  in iop3xx_aau_desc_set_src_addr()
445 	struct iop3xx_desc_dma *hw_desc = desc->hw_desc;  in iop_desc_init_memcpy()
455 	hw_desc->desc_ctrl = u_desc_ctrl.value;  in iop_desc_init_memcpy()
456 	hw_desc->upper_pci_src_addr = 0;  in iop_desc_init_memcpy()
457 	hw_desc->crc_addr = 0;  in iop_desc_init_memcpy()
463 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc;  in iop_desc_init_memset()
473 	hw_desc->desc_ctrl = u_desc_ctrl.value;  in iop_desc_init_memset()
497 		hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;  in iop3xx_desc_init_xor()
502 			hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;  in iop3xx_desc_init_xor()
511 		hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;  in iop3xx_desc_init_xor()
523 		hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;  in iop3xx_desc_init_xor()
534 			u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */  in iop3xx_desc_init_xor()
540 	hw_desc->desc_ctrl = u_desc_ctrl.value;  in iop3xx_desc_init_xor()
549 	iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags);  in iop_desc_init_xor()
557 	int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;  in iop_desc_init_zero_sum()
565 	hw_desc = desc->hw_desc;  in iop_desc_init_zero_sum()
567 	for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;  in iop_desc_init_zero_sum()
574 		iter->desc_ctrl = u_desc_ctrl.value;  in iop_desc_init_zero_sum()
581 				iop_hw_desc_slot_idx(hw_desc, i - slots_per_op);  in iop_desc_init_zero_sum()
582 			prev_hw_desc->next_desc =  in iop_desc_init_zero_sum()
583 				(u32) (desc->async_tx.phys + (i << 5));  in iop_desc_init_zero_sum()
594 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc;  in iop_desc_init_null_xor()
604 		hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;  in iop_desc_init_null_xor()
608 			hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;  in iop_desc_init_null_xor()
611 		hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;  in iop_desc_init_null_xor()
616 		hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;  in iop_desc_init_null_xor()
620 			u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */  in iop_desc_init_null_xor()
625 	hw_desc->desc_ctrl = u_desc_ctrl.value;  in iop_desc_init_null_xor()
632 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_set_byte_count()
634 	switch (chan->device->id) {  in iop_desc_set_byte_count()
637 		hw_desc.dma->byte_count = byte_count;  in iop_desc_set_byte_count()
640 		hw_desc.aau->byte_count = byte_count;  in iop_desc_set_byte_count()
651 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_init_interrupt()
653 	switch (chan->device->id) {  in iop_desc_init_interrupt()
657 		hw_desc.dma->byte_count = 0;  in iop_desc_init_interrupt()
658 		hw_desc.dma->dest_addr = 0;  in iop_desc_init_interrupt()
659 		hw_desc.dma->src_addr = 0;  in iop_desc_init_interrupt()
663 		hw_desc.aau->byte_count = 0;  in iop_desc_init_interrupt()
664 		hw_desc.aau->dest_addr = 0;  in iop_desc_init_interrupt()
665 		hw_desc.aau->src[0] = 0;  in iop_desc_init_interrupt()
666 		hw_desc.aau->src[1] = 0;  in iop_desc_init_interrupt()
676 	int slots_per_op = desc->slots_per_op;  in iop_desc_set_zero_sum_byte_count()
677 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;  in iop_desc_set_zero_sum_byte_count()
681 		hw_desc->byte_count = len;  in iop_desc_set_zero_sum_byte_count()
685 			iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;  in iop_desc_set_zero_sum_byte_count()
686 			len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;  in iop_desc_set_zero_sum_byte_count()
691 		iter->byte_count = len;  in iop_desc_set_zero_sum_byte_count()
699 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_set_dest_addr()
701 	switch (chan->device->id) {  in iop_desc_set_dest_addr()
704 		hw_desc.dma->dest_addr = addr;  in iop_desc_set_dest_addr()
707 		hw_desc.aau->dest_addr = addr;  in iop_desc_set_dest_addr()
717 	struct iop3xx_desc_dma *hw_desc = desc->hw_desc;  in iop_desc_set_memcpy_src_addr()
718 	hw_desc->src_addr = addr;  in iop_desc_set_memcpy_src_addr()
726 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;  in iop_desc_set_zero_sum_src_addr()
727 	int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;  in iop_desc_set_zero_sum_src_addr()
730 	for (i = 0; (slot_cnt -= slots_per_op) >= 0;  in iop_desc_set_zero_sum_src_addr()
741 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;  in iop_desc_set_xor_src_addr()
742 	int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;  in iop_desc_set_xor_src_addr()
745 	for (i = 0; (slot_cnt -= slots_per_op) >= 0;  in iop_desc_set_xor_src_addr()
755 	/* hw_desc->next_desc is the same location for all channels */  in iop_desc_set_next_desc()
756 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_set_next_desc()
758 	iop_paranoia(hw_desc.dma->next_desc);  in iop_desc_set_next_desc()
759 	hw_desc.dma->next_desc = next_desc_addr;  in iop_desc_set_next_desc()
764 	/* hw_desc->next_desc is the same location for all channels */  in iop_desc_get_next_desc()
765 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_get_next_desc()
766 	return hw_desc.dma->next_desc;  in iop_desc_get_next_desc()
771 	/* hw_desc->next_desc is the same location for all channels */  in iop_desc_clear_next_desc()
772 	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };  in iop_desc_clear_next_desc()
773 	hw_desc.dma->next_desc = 0;  in iop_desc_clear_next_desc()
779 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc;  in iop_desc_set_block_fill_val()
780 	hw_desc->src[0] = val;  in iop_desc_set_block_fill_val()
786 	struct iop3xx_desc_aau *hw_desc = desc->hw_desc;  in iop_desc_get_zero_result()
787 	struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;  in iop_desc_get_zero_result()
840 	switch (chan->device->id) {  in iop_adma_device_clear_err_status()
882 	switch (chan->device->id) {  in iop_is_err_pci_tabort()
894 	switch (chan->device->id) {  in iop_is_err_pci_mabort()
906 	switch (chan->device->id) {  in iop_is_err_split_tx()