Lines Matching +full:src +full:- +full:coef
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
129 * This is the function to change channel on single-chip devices, that is
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
187 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
223 ah->curchan = chan; in ar9003_hw_set_channel()
229 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
233 * For single-chip solutions. Converts to baseband spur frequency given the
248 * Need to verify range +/- 10 MHz in control channel, otherwise spur in ar9003_hw_spur_mitigate_mrc_cck()
249 * is out-of-band and can be ignored. in ar9003_hw_spur_mitigate_mrc_cck()
261 synth_freq = chan->channel + 10; in ar9003_hw_spur_mitigate_mrc_cck()
263 synth_freq = chan->channel - 10; in ar9003_hw_spur_mitigate_mrc_cck()
266 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_mrc_cck()
271 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_mrc_cck()
286 cur_bb_spur -= synth_freq; in ar9003_hw_spur_mitigate_mrc_cck()
289 cur_bb_spur = -cur_bb_spur; in ar9003_hw_spur_mitigate_mrc_cck()
295 cck_spur_freq = -cck_spur_freq; in ar9003_hw_spur_mitigate_mrc_cck()
410 mask_index = mask_index - 1; in ar9003_hw_spur_ofdm()
443 mask_index = mask_index - 1; in ar9003_hw_spur_ofdm_9565()
496 spur_freq_sd = ((freq_offset - 10) << 9) / 11; in ar9003_hw_spur_ofdm_work()
529 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_spur_mitigate_ofdm()
532 spurChansPtr = &(eep->modalHeader5G.spurChans[0]); in ar9003_hw_spur_mitigate_ofdm()
536 spurChansPtr = &(eep->modalHeader2G.spurChans[0]); in ar9003_hw_spur_mitigate_ofdm()
547 synth_freq = chan->channel - 10; in ar9003_hw_spur_mitigate_ofdm()
549 synth_freq = chan->channel + 10; in ar9003_hw_spur_mitigate_ofdm()
552 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_ofdm()
559 freq_offset -= synth_freq; in ar9003_hw_spur_mitigate_ofdm()
567 freq_offset -= synth_freq; in ar9003_hw_spur_mitigate_ofdm()
637 /* Configure control (primary) channel at +-10MHz */ in ar9003_hw_set_channel_regs()
678 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
685 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
724 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
726 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
731 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
733 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
737 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
757 if (!iniArr->ia_array) in ar9003_hw_prog_ini()
762 * may be modal (> 2 columns) or non-modal (2 columns). Determine if in ar9003_hw_prog_ini()
763 * the array is non-modal and force the column to 1. in ar9003_hw_prog_ini()
765 if (column >= iniArr->ia_columns) in ar9003_hw_prog_ini()
768 for (i = 0; i < iniArr->ia_rows; i++) { in ar9003_hw_prog_ini()
790 if (chan->channel <= 5350) in ar9550_hw_get_modes_txgain_index()
792 else if ((chan->channel > 5350) && (chan->channel <= 5600)) in ar9550_hw_get_modes_txgain_index()
879 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
880 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
881 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
882 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
885 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
894 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
901 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
908 * 5G-XLNA in ar9003_hw_process_ini()
912 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
918 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
922 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
938 return -EINVAL; in ar9003_hw_process_ini()
940 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
943 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
951 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
957 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
962 if (chan->channel == 2484) { in ar9003_hw_process_ini()
963 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
970 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
973 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
1024 * ALGO -> coef = 1e8/fcarrier*fclock/40; in ar9003_hw_set_delta_slope()
1025 * scaled coef to provide precision for this floating calculation in ar9003_hw_set_delta_slope()
1069 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
1078 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
1079 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
1087 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1102 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; in ar9003_hw_ani_control()
1104 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; in ar9003_hw_ani_control()
1106 aniState->iniDef.m1Thresh : m1Thresh_off; in ar9003_hw_ani_control()
1108 aniState->iniDef.m2Thresh : m2Thresh_off; in ar9003_hw_ani_control()
1110 aniState->iniDef.m2CountThr : m2CountThr_off; in ar9003_hw_ani_control()
1112 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; in ar9003_hw_ani_control()
1114 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; in ar9003_hw_ani_control()
1116 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; in ar9003_hw_ani_control()
1118 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; in ar9003_hw_ani_control()
1120 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; in ar9003_hw_ani_control()
1160 if (on != aniState->ofdmWeakSigDetect) { in ar9003_hw_ani_control()
1163 chan->channel, in ar9003_hw_ani_control()
1164 aniState->ofdmWeakSigDetect ? in ar9003_hw_ani_control()
1168 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1170 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1171 aniState->ofdmWeakSigDetect = on; in ar9003_hw_ani_control()
1189 value = firstep_table[level] - in ar9003_hw_ani_control()
1191 aniState->iniDef.firstep; in ar9003_hw_ani_control()
1204 value2 = firstep_table[level] - in ar9003_hw_ani_control()
1206 aniState->iniDef.firstepLow; in ar9003_hw_ani_control()
1215 if (level != aniState->firstepLevel) { in ar9003_hw_ani_control()
1218 chan->channel, in ar9003_hw_ani_control()
1219 aniState->firstepLevel, in ar9003_hw_ani_control()
1223 aniState->iniDef.firstep); in ar9003_hw_ani_control()
1226 chan->channel, in ar9003_hw_ani_control()
1227 aniState->firstepLevel, in ar9003_hw_ani_control()
1231 aniState->iniDef.firstepLow); in ar9003_hw_ani_control()
1232 if (level > aniState->firstepLevel) in ar9003_hw_ani_control()
1233 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1234 else if (level < aniState->firstepLevel) in ar9003_hw_ani_control()
1235 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1236 aniState->firstepLevel = level; in ar9003_hw_ani_control()
1253 value = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1255 aniState->iniDef.cycpwrThr1; in ar9003_hw_ani_control()
1269 value2 = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1271 aniState->iniDef.cycpwrThr1Ext; in ar9003_hw_ani_control()
1279 if (level != aniState->spurImmunityLevel) { in ar9003_hw_ani_control()
1282 chan->channel, in ar9003_hw_ani_control()
1283 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1287 aniState->iniDef.cycpwrThr1); in ar9003_hw_ani_control()
1290 chan->channel, in ar9003_hw_ani_control()
1291 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1295 aniState->iniDef.cycpwrThr1Ext); in ar9003_hw_ani_control()
1296 if (level > aniState->spurImmunityLevel) in ar9003_hw_ani_control()
1297 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1298 else if (level < aniState->spurImmunityLevel) in ar9003_hw_ani_control()
1299 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1300 aniState->spurImmunityLevel = level; in ar9003_hw_ani_control()
1311 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1318 if (is_on != aniState->mrcCCK) { in ar9003_hw_ani_control()
1320 chan->channel, in ar9003_hw_ani_control()
1321 aniState->mrcCCK ? "on" : "off", in ar9003_hw_ani_control()
1324 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1326 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1327 aniState->mrcCCK = is_on; in ar9003_hw_ani_control()
1338 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1339 aniState->ofdmWeakSigDetect ? "on" : "off", in ar9003_hw_ani_control()
1340 aniState->firstepLevel, in ar9003_hw_ani_control()
1341 aniState->mrcCCK ? "on" : "off", in ar9003_hw_ani_control()
1342 aniState->listenTime, in ar9003_hw_ani_control()
1343 aniState->ofdmPhyErrCount, in ar9003_hw_ani_control()
1344 aniState->cckPhyErrCount); in ar9003_hw_ani_control()
1360 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1361 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1365 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1368 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1378 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1379 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1380 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1381 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1382 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1383 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1386 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1389 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1390 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1391 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1392 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1405 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1409 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1410 iniDef = &aniState->iniDef; in ar9003_hw_ani_cache_ini_regs()
1413 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1414 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1415 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1416 chan->channel); in ar9003_hw_ani_cache_ini_regs()
1419 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1420 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1421 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); in ar9003_hw_ani_cache_ini_regs()
1424 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1425 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1426 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); in ar9003_hw_ani_cache_ini_regs()
1429 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1430 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1431 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1432 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1433 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1436 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1439 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1442 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1447 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; in ar9003_hw_ani_cache_ini_regs()
1448 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; in ar9003_hw_ani_cache_ini_regs()
1449 aniState->ofdmWeakSigDetect = true; in ar9003_hw_ani_cache_ini_regs()
1450 aniState->mrcCCK = true; in ar9003_hw_ani_cache_ini_regs()
1465 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1466 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
1467 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); in ar9003_hw_set_radar_params()
1468 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); in ar9003_hw_set_radar_params()
1469 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); in ar9003_hw_set_radar_params()
1476 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); in ar9003_hw_set_radar_params()
1477 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); in ar9003_hw_set_radar_params()
1478 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); in ar9003_hw_set_radar_params()
1482 if (conf->ext_channel) in ar9003_hw_set_radar_params()
1488 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1489 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1495 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1497 conf->fir_power = -28; in ar9003_hw_set_radar_conf()
1498 conf->radar_rssi = 0; in ar9003_hw_set_radar_conf()
1499 conf->pulse_height = 10; in ar9003_hw_set_radar_conf()
1500 conf->pulse_rssi = 15; in ar9003_hw_set_radar_conf()
1501 conf->pulse_inband = 8; in ar9003_hw_set_radar_conf()
1502 conf->pulse_maxlen = 255; in ar9003_hw_set_radar_conf()
1503 conf->pulse_inband_step = 12; in ar9003_hw_set_radar_conf()
1504 conf->radar_inband = 8; in ar9003_hw_set_radar_conf()
1513 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1515 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1517 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> in ar9003_hw_antdiv_comb_conf_get()
1521 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1522 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1523 antconf->div_group = 1; in ar9003_hw_antdiv_comb_conf_get()
1525 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1526 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1527 antconf->div_group = 2; in ar9003_hw_antdiv_comb_conf_get()
1529 antconf->lna1_lna2_switch_delta = 3; in ar9003_hw_antdiv_comb_conf_get()
1530 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1531 antconf->div_group = 3; in ar9003_hw_antdiv_comb_conf_get()
1533 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1534 antconf->lna1_lna2_delta = -3; in ar9003_hw_antdiv_comb_conf_get()
1535 antconf->div_group = 0; in ar9003_hw_antdiv_comb_conf_get()
1550 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1552 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1554 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) in ar9003_hw_antdiv_comb_conf_set()
1556 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) in ar9003_hw_antdiv_comb_conf_set()
1558 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) in ar9003_hw_antdiv_comb_conf_set()
1568 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1577 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1580 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1586 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1620 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_set_bt_ant_diversity()
1690 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1695 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1696 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1697 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1698 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1701 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1704 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1711 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1713 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1723 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1726 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1731 if (chan->channel == 2484) in ar9003_hw_fast_chan_change()
1732 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1734 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1747 if (!param->enabled) { in ar9003_hw_spectral_scan_config()
1760 count = param->count; in ar9003_hw_spectral_scan_config()
1761 if (param->endless) in ar9003_hw_spectral_scan_config()
1763 else if (param->count == 0) in ar9003_hw_spectral_scan_config()
1766 if (param->short_repeat) in ar9003_hw_spectral_scan_config()
1776 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); in ar9003_hw_spectral_scan_config()
1778 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); in ar9003_hw_spectral_scan_config()
1838 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1839 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1840 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], in ar9003_hw_init_txpower_cck()
1842 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], in ar9003_hw_init_txpower_cck()
1853 j = ofdm2pwr[i - offset]; in ar9003_hw_init_txpower_ofdm()
1854 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ofdm()
1867 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1873 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1879 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1887 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], in ar9003_hw_init_txpower_stbc()
1889 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], in ar9003_hw_init_txpower_stbc()
1891 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], in ar9003_hw_init_txpower_stbc()
1943 priv_ops->rf_set_freq = ar9003_hw_set_channel; in ar9003_hw_attach_phy_ops()
1944 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; in ar9003_hw_attach_phy_ops()
1948 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; in ar9003_hw_attach_phy_ops()
1950 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; in ar9003_hw_attach_phy_ops()
1952 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; in ar9003_hw_attach_phy_ops()
1953 priv_ops->init_bb = ar9003_hw_init_bb; in ar9003_hw_attach_phy_ops()
1954 priv_ops->process_ini = ar9003_hw_process_ini; in ar9003_hw_attach_phy_ops()
1955 priv_ops->set_rfmode = ar9003_hw_set_rfmode; in ar9003_hw_attach_phy_ops()
1956 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; in ar9003_hw_attach_phy_ops()
1957 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; in ar9003_hw_attach_phy_ops()
1958 priv_ops->rfbus_req = ar9003_hw_rfbus_req; in ar9003_hw_attach_phy_ops()
1959 priv_ops->rfbus_done = ar9003_hw_rfbus_done; in ar9003_hw_attach_phy_ops()
1960 priv_ops->ani_control = ar9003_hw_ani_control; in ar9003_hw_attach_phy_ops()
1961 priv_ops->do_getnf = ar9003_hw_do_getnf; in ar9003_hw_attach_phy_ops()
1962 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; in ar9003_hw_attach_phy_ops()
1963 priv_ops->set_radar_params = ar9003_hw_set_radar_params; in ar9003_hw_attach_phy_ops()
1964 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; in ar9003_hw_attach_phy_ops()
1966 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; in ar9003_hw_attach_phy_ops()
1967 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; in ar9003_hw_attach_phy_ops()
1968 ops->spectral_scan_config = ar9003_hw_spectral_scan_config; in ar9003_hw_attach_phy_ops()
1969 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; in ar9003_hw_attach_phy_ops()
1970 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; in ar9003_hw_attach_phy_ops()
1973 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity; in ar9003_hw_attach_phy_ops()
1975 ops->tx99_start = ar9003_hw_tx99_start; in ar9003_hw_attach_phy_ops()
1976 ops->tx99_stop = ar9003_hw_tx99_stop; in ar9003_hw_attach_phy_ops()
1977 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower; in ar9003_hw_attach_phy_ops()
1981 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
2014 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
2050 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
2054 /* disable IRQ, disable chip-reset for BB panic */ in ar9003_hw_bb_watchdog_config()
2060 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ in ar9003_hw_bb_watchdog_config()
2070 /* enable IRQ, disable chip-reset for BB watchdog */ in ar9003_hw_bb_watchdog_config()
2090 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
2094 * enable watchdog in non-IDLE mode, disable in IDLE mode, in ar9003_hw_bb_watchdog_config()
2095 * set idle time-out. in ar9003_hw_bb_watchdog_config()
2112 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
2119 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
2127 if (likely(!(common->debug_mask & ATH_DBG_RESET))) in ar9003_hw_bb_watchdog_dbg_info()
2130 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2134 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", in ar9003_hw_bb_watchdog_dbg_info()
2151 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) in ar9003_hw_bb_watchdog_dbg_info()
2152 if (common->cc_survey.cycles) in ar9003_hw_bb_watchdog_dbg_info()
2171 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2173 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2174 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()