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/Linux-v6.6/Documentation/devicetree/bindings/riscv/
Dcpus.yaml4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
50 - const: riscv
56 - const: riscv
57 - const: riscv # Simulator only
67 https://riscv.org/specifications/
70 - riscv,sv32
71 - riscv,sv39
72 - riscv,sv48
73 - riscv,sv57
74 - riscv,none
[all …]
Dextensions.yaml4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
31 const: riscv
34 riscv,isa:
39 https://riscv.org/specifications/
43 Notably, riscv,isa was defined prior to the creation of the
48 insensitive, letters in the riscv,isa string must be all
54 riscv,isa-base:
62 riscv,isa-extensions:
116 encoding") of the riscv-v-spec.
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
[all …]
/Linux-v6.6/drivers/gpu/drm/tegra/
Driscv.c11 #include "riscv.h"
32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
[all …]
Dnvdec.c22 #include "riscv.h"
51 struct tegra_drm_riscv riscv; member
118 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1, in nvdec_boot_riscv()
119 &nvdec->riscv.bl_desc); in nvdec_boot_riscv()
135 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1, in nvdec_boot_riscv()
136 &nvdec->riscv.os_desc); in nvdec_boot_riscv()
500 nvdec->riscv.dev = dev; in nvdec_probe()
501 nvdec->riscv.regs = nvdec->regs; in nvdec_probe()
503 err = tegra_drm_riscv_read_descriptors(&nvdec->riscv); in nvdec_probe()
/Linux-v6.6/arch/riscv/
DMakefile58 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
59 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
60 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
61 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
62 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
68 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
72 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
76 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\…
78 KBUILD_AFLAGS += -march=$(riscv-march-y)
95 KBUILD_CFLAGS += $(call cc-option,-mno-riscv-attribute)
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/perf/
Driscv,pmu.yaml4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
35 const: riscv,pmu
37 riscv,event-to-mhpmevent:
54 riscv,event-to-mhpmcounters:
68 riscv,raw-event-to-mhpmcounters:
93 "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ]
103 compatible = "riscv,pmu";
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
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/Linux-v6.6/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
36 compatible = "riscv,cpu-intc";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
53 mmu-type = "riscv,sv39";
55 riscv,isa = "rv64imafdc";
60 compatible = "riscv,cpu-intc";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
77 mmu-type = "riscv,sv39";
79 riscv,isa = "rv64imafdc";
[all …]
Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
37 compatible = "riscv,cpu-intc";
42 compatible = "sifive,bullet0", "riscv";
54 mmu-type = "riscv,sv39";
57 riscv,isa = "rv64imafdc";
61 compatible = "riscv,cpu-intc";
66 compatible = "sifive,bullet0", "riscv";
78 mmu-type = "riscv,sv39";
81 riscv,isa = "rv64imafdc";
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/cpu/
Didle-states.yaml265 Documentation/devicetree/bindings/riscv/cpus.yaml
268 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
306 - riscv,idle-state
317 riscv,sbi-suspend-param:
718 compatible = "riscv";
720 riscv,isa = "rv64imafdc";
721 mmu-type = "riscv,sv48";
727 compatible = "riscv,cpu-intc";
734 compatible = "riscv";
736 riscv,isa = "rv64imafdc";
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/Linux-v6.6/arch/riscv/kernel/
Dcpu.c53 if (!of_device_is_compatible(node, "riscv")) { in riscv_early_of_processor_hartid()
69 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
82 if (!of_property_present(node, "riscv,isa-extensions")) in riscv_early_of_processor_hartid()
85 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 || in riscv_early_of_processor_hartid()
86 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 || in riscv_early_of_processor_hartid()
87 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) { in riscv_early_of_processor_hartid()
96 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"", in riscv_early_of_processor_hartid()
101 if (of_property_read_string(node, "riscv,isa", &isa)) { in riscv_early_of_processor_hartid()
102 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", in riscv_early_of_processor_hartid()
131 if (of_device_is_compatible(node, "riscv")) { in riscv_of_parent_hartid()
[all …]
/Linux-v6.6/arch/riscv/boot/dts/thead/
Dth1520.dtsi20 compatible = "thead,c910", "riscv";
22 riscv,isa = "rv64imafdc";
31 mmu-type = "riscv,sv39";
34 compatible = "riscv,cpu-intc";
41 compatible = "thead,c910", "riscv";
43 riscv,isa = "rv64imafdc";
52 mmu-type = "riscv,sv39";
55 compatible = "riscv,cpu-intc";
62 compatible = "thead,c910", "riscv";
64 riscv,isa = "rv64imafdc";
[all …]
/Linux-v6.6/drivers/clocksource/
Dtimer-riscv.c11 #define pr_fmt(fmt) "riscv-timer: " fmt
25 #include <clocksource/timer-riscv.h>
149 pr_err("RISCV timer registration failed [%d]\n", error); in riscv_timer_init_common()
157 "riscv-timer", &riscv_clock_event); in riscv_timer_init_common()
169 "clockevents/riscv/timer:starting", in riscv_timer_init_common()
172 pr_err("cpu hp setup state failed for RISCV timer [%d]\n", in riscv_timer_init_common()
200 child = of_find_compatible_node(NULL, NULL, "riscv,timer"); in riscv_timer_init_dt()
203 "riscv,timer-cannot-wake-cpu"); in riscv_timer_init_dt()
210 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);
/Linux-v6.6/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
24 riscv,isa = "rv64imac";
30 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
48 mmu-type = "riscv,sv39";
50 riscv,isa = "rv64imafdc";
58 compatible = "riscv,cpu-intc";
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
76 mmu-type = "riscv,sv39";
78 riscv,isa = "rv64imafdc";
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml4 $id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
20 in Documentation/devicetree/bindings/riscv/cpus.yaml
25 - riscv,timer
31 riscv,timer-cannot-wake-cpu:
46 compatible = "riscv,timer";
/Linux-v6.6/arch/riscv/boot/dts/renesas/
Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 mmu-type = "riscv,sv39";
37 compatible = "riscv,cpu-intc";
51 riscv,ndev = <511>;
/Linux-v6.6/Documentation/riscv/
Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/Linux-v6.6/tools/testing/kunit/qemu_configs/
Driscv.py11 …'Please ensure that qemu-system-riscv is installed, or edit the path in "qemu_configs/riscv.py"\n')
14 QEMU_ARCH = QemuArchParams(linux_arch='riscv',
23 kernel_path='arch/riscv/boot/Image',
/Linux-v6.6/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
31 compatible = "riscv,cpu-intc";
71 riscv,ndev = <175>;
/Linux-v6.6/arch/riscv/boot/dts/starfive/
Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
34 mmu-type = "riscv,sv39";
35 riscv,isa = "rv64imafdc";
39 compatible = "riscv,cpu-intc";
46 compatible = "sifive,u74-mc", "riscv";
59 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
64 compatible = "riscv,cpu-intc";
158 riscv,ndev = <133>;
Djh7110.dtsi23 compatible = "sifive,s7", "riscv";
30 riscv,isa = "rv64imac_zba_zbb";
34 compatible = "riscv,cpu-intc";
41 compatible = "sifive,u74-mc", "riscv";
54 mmu-type = "riscv,sv39";
56 riscv,isa = "rv64imafdc_zba_zbb";
64 compatible = "riscv,cpu-intc";
71 compatible = "sifive,u74-mc", "riscv";
84 mmu-type = "riscv,sv39";
86 riscv,isa = "rv64imafdc_zba_zbb";
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml72 - const: riscv,plic0
92 riscv,cpu-intc node, which has a riscv node as parent.
94 riscv,ndev:
112 - riscv,ndev
170 riscv,ndev = <10>;
/Linux-v6.6/drivers/clk/sunxi-ng/
DKconfig18 depends on MACH_SUN8I || RISCV || COMPILE_TEST
23 depends on MACH_SUN8I || RISCV || COMPILE_TEST
74 depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
104 depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST
/Linux-v6.6/arch/riscv/purgatory/
DMakefile16 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
19 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
22 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
25 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
28 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE
/Linux-v6.6/arch/riscv/include/asm/
Dgdb_xml.h13 "qXfer:features:read:riscv-64bit-cpu.xml";
19 "<xi:include href=\"riscv-64bit-cpu.xml\"/>"
25 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
65 "qXfer:features:read:riscv-32bit-cpu.xml";
71 "<xi:include href=\"riscv-32bit-cpu.xml\"/>"
77 "<feature name=\"org.gnu.gdb.riscv.cpu\">"
/Linux-v6.6/tools/testing/selftests/rseq/
Drseq-riscv.h172 #include "rseq-riscv-bits.h"
176 #include "rseq-riscv-bits.h"
184 #include "rseq-riscv-bits.h"
188 #include "rseq-riscv-bits.h"
196 #include "rseq-riscv-bits.h"

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