Lines Matching full:riscv

4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
31         const: riscv
34   riscv,isa:
39       https://riscv.org/specifications/
43       Notably, riscv,isa was defined prior to the creation of the
48       insensitive, letters in the riscv,isa string must be all
54   riscv,isa-base:
62   riscv,isa-extensions:
116             encoding") of the riscv-v-spec.
129             request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
136             ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
142             to manually trigger workflow. (#2)") of riscv-count-overflow.
148             workflow. (#2)") of riscv-time-compare.
173             riscv-bitmanip.
179             hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
185             #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
191             from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
196             ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
202             riscv-CMOs.
207             in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
235             commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
247             riscv-isa-manual.