1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4/dts-v1/; 5#include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7/ { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 clocks = <&clkcfg CLK_CPU>; 26 status = "disabled"; 27 28 cpu0_intc: interrupt-controller { 29 #interrupt-cells = <1>; 30 compatible = "riscv,cpu-intc"; 31 interrupt-controller; 32 }; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 clocks = <&clkcfg CLK_CPU>; 52 tlb-split; 53 next-level-cache = <&cctrllr>; 54 status = "okay"; 55 56 cpu1_intc: interrupt-controller { 57 #interrupt-cells = <1>; 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 65 d-cache-block-size = <64>; 66 d-cache-sets = <64>; 67 d-cache-size = <32768>; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 70 device_type = "cpu"; 71 i-cache-block-size = <64>; 72 i-cache-sets = <64>; 73 i-cache-size = <32768>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 76 mmu-type = "riscv,sv39"; 77 reg = <2>; 78 riscv,isa = "rv64imafdc"; 79 clocks = <&clkcfg CLK_CPU>; 80 tlb-split; 81 next-level-cache = <&cctrllr>; 82 status = "okay"; 83 84 cpu2_intc: interrupt-controller { 85 #interrupt-cells = <1>; 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 }; 89 }; 90 91 cpu3: cpu@3 { 92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 93 d-cache-block-size = <64>; 94 d-cache-sets = <64>; 95 d-cache-size = <32768>; 96 d-tlb-sets = <1>; 97 d-tlb-size = <32>; 98 device_type = "cpu"; 99 i-cache-block-size = <64>; 100 i-cache-sets = <64>; 101 i-cache-size = <32768>; 102 i-tlb-sets = <1>; 103 i-tlb-size = <32>; 104 mmu-type = "riscv,sv39"; 105 reg = <3>; 106 riscv,isa = "rv64imafdc"; 107 clocks = <&clkcfg CLK_CPU>; 108 tlb-split; 109 next-level-cache = <&cctrllr>; 110 status = "okay"; 111 112 cpu3_intc: interrupt-controller { 113 #interrupt-cells = <1>; 114 compatible = "riscv,cpu-intc"; 115 interrupt-controller; 116 }; 117 }; 118 119 cpu4: cpu@4 { 120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 121 d-cache-block-size = <64>; 122 d-cache-sets = <64>; 123 d-cache-size = <32768>; 124 d-tlb-sets = <1>; 125 d-tlb-size = <32>; 126 device_type = "cpu"; 127 i-cache-block-size = <64>; 128 i-cache-sets = <64>; 129 i-cache-size = <32768>; 130 i-tlb-sets = <1>; 131 i-tlb-size = <32>; 132 mmu-type = "riscv,sv39"; 133 reg = <4>; 134 riscv,isa = "rv64imafdc"; 135 clocks = <&clkcfg CLK_CPU>; 136 tlb-split; 137 next-level-cache = <&cctrllr>; 138 status = "okay"; 139 cpu4_intc: interrupt-controller { 140 #interrupt-cells = <1>; 141 compatible = "riscv,cpu-intc"; 142 interrupt-controller; 143 }; 144 }; 145 146 cpu-map { 147 cluster0 { 148 core0 { 149 cpu = <&cpu0>; 150 }; 151 152 core1 { 153 cpu = <&cpu1>; 154 }; 155 156 core2 { 157 cpu = <&cpu2>; 158 }; 159 160 core3 { 161 cpu = <&cpu3>; 162 }; 163 164 core4 { 165 cpu = <&cpu4>; 166 }; 167 }; 168 }; 169 }; 170 171 refclk: mssrefclk { 172 compatible = "fixed-clock"; 173 #clock-cells = <0>; 174 }; 175 176 syscontroller: syscontroller { 177 compatible = "microchip,mpfs-sys-controller"; 178 mboxes = <&mbox 0>; 179 }; 180 181 soc { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 compatible = "simple-bus"; 185 ranges; 186 187 cctrllr: cache-controller@2010000 { 188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; 189 reg = <0x0 0x2010000 0x0 0x1000>; 190 cache-block-size = <64>; 191 cache-level = <2>; 192 cache-sets = <1024>; 193 cache-size = <2097152>; 194 cache-unified; 195 interrupt-parent = <&plic>; 196 interrupts = <1>, <3>, <4>, <2>; 197 }; 198 199 clint: clint@2000000 { 200 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 201 reg = <0x0 0x2000000 0x0 0xC000>; 202 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 203 <&cpu1_intc 3>, <&cpu1_intc 7>, 204 <&cpu2_intc 3>, <&cpu2_intc 7>, 205 <&cpu3_intc 3>, <&cpu3_intc 7>, 206 <&cpu4_intc 3>, <&cpu4_intc 7>; 207 }; 208 209 plic: interrupt-controller@c000000 { 210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 211 reg = <0x0 0xc000000 0x0 0x4000000>; 212 #address-cells = <0>; 213 #interrupt-cells = <1>; 214 interrupt-controller; 215 interrupts-extended = <&cpu0_intc 11>, 216 <&cpu1_intc 11>, <&cpu1_intc 9>, 217 <&cpu2_intc 11>, <&cpu2_intc 9>, 218 <&cpu3_intc 11>, <&cpu3_intc 9>, 219 <&cpu4_intc 11>, <&cpu4_intc 9>; 220 riscv,ndev = <186>; 221 }; 222 223 pdma: dma-controller@3000000 { 224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; 225 reg = <0x0 0x3000000 0x0 0x8000>; 226 interrupt-parent = <&plic>; 227 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 228 dma-channels = <4>; 229 #dma-cells = <1>; 230 }; 231 232 clkcfg: clkcfg@20002000 { 233 compatible = "microchip,mpfs-clkcfg"; 234 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 235 clocks = <&refclk>; 236 #clock-cells = <1>; 237 #reset-cells = <1>; 238 }; 239 240 ccc_se: clock-controller@38010000 { 241 compatible = "microchip,mpfs-ccc"; 242 reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, 243 <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; 244 #clock-cells = <1>; 245 status = "disabled"; 246 }; 247 248 ccc_ne: clock-controller@38040000 { 249 compatible = "microchip,mpfs-ccc"; 250 reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, 251 <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; 252 #clock-cells = <1>; 253 status = "disabled"; 254 }; 255 256 ccc_nw: clock-controller@38100000 { 257 compatible = "microchip,mpfs-ccc"; 258 reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, 259 <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; 260 #clock-cells = <1>; 261 status = "disabled"; 262 }; 263 264 ccc_sw: clock-controller@38400000 { 265 compatible = "microchip,mpfs-ccc"; 266 reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, 267 <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; 268 #clock-cells = <1>; 269 status = "disabled"; 270 }; 271 272 mmuart0: serial@20000000 { 273 compatible = "ns16550a"; 274 reg = <0x0 0x20000000 0x0 0x400>; 275 reg-io-width = <4>; 276 reg-shift = <2>; 277 interrupt-parent = <&plic>; 278 interrupts = <90>; 279 current-speed = <115200>; 280 clocks = <&clkcfg CLK_MMUART0>; 281 status = "disabled"; /* Reserved for the HSS */ 282 }; 283 284 mmuart1: serial@20100000 { 285 compatible = "ns16550a"; 286 reg = <0x0 0x20100000 0x0 0x400>; 287 reg-io-width = <4>; 288 reg-shift = <2>; 289 interrupt-parent = <&plic>; 290 interrupts = <91>; 291 current-speed = <115200>; 292 clocks = <&clkcfg CLK_MMUART1>; 293 status = "disabled"; 294 }; 295 296 mmuart2: serial@20102000 { 297 compatible = "ns16550a"; 298 reg = <0x0 0x20102000 0x0 0x400>; 299 reg-io-width = <4>; 300 reg-shift = <2>; 301 interrupt-parent = <&plic>; 302 interrupts = <92>; 303 current-speed = <115200>; 304 clocks = <&clkcfg CLK_MMUART2>; 305 status = "disabled"; 306 }; 307 308 mmuart3: serial@20104000 { 309 compatible = "ns16550a"; 310 reg = <0x0 0x20104000 0x0 0x400>; 311 reg-io-width = <4>; 312 reg-shift = <2>; 313 interrupt-parent = <&plic>; 314 interrupts = <93>; 315 current-speed = <115200>; 316 clocks = <&clkcfg CLK_MMUART3>; 317 status = "disabled"; 318 }; 319 320 mmuart4: serial@20106000 { 321 compatible = "ns16550a"; 322 reg = <0x0 0x20106000 0x0 0x400>; 323 reg-io-width = <4>; 324 reg-shift = <2>; 325 interrupt-parent = <&plic>; 326 interrupts = <94>; 327 clocks = <&clkcfg CLK_MMUART4>; 328 current-speed = <115200>; 329 status = "disabled"; 330 }; 331 332 /* Common node entry for emmc/sd */ 333 mmc: mmc@20008000 { 334 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 335 reg = <0x0 0x20008000 0x0 0x1000>; 336 interrupt-parent = <&plic>; 337 interrupts = <88>; 338 clocks = <&clkcfg CLK_MMC>; 339 max-frequency = <200000000>; 340 status = "disabled"; 341 }; 342 343 spi0: spi@20108000 { 344 compatible = "microchip,mpfs-spi"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 reg = <0x0 0x20108000 0x0 0x1000>; 348 interrupt-parent = <&plic>; 349 interrupts = <54>; 350 clocks = <&clkcfg CLK_SPI0>; 351 status = "disabled"; 352 }; 353 354 spi1: spi@20109000 { 355 compatible = "microchip,mpfs-spi"; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 reg = <0x0 0x20109000 0x0 0x1000>; 359 interrupt-parent = <&plic>; 360 interrupts = <55>; 361 clocks = <&clkcfg CLK_SPI1>; 362 status = "disabled"; 363 }; 364 365 qspi: spi@21000000 { 366 compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; 367 #address-cells = <1>; 368 #size-cells = <0>; 369 reg = <0x0 0x21000000 0x0 0x1000>; 370 interrupt-parent = <&plic>; 371 interrupts = <85>; 372 clocks = <&clkcfg CLK_QSPI>; 373 status = "disabled"; 374 }; 375 376 i2c0: i2c@2010a000 { 377 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 378 reg = <0x0 0x2010a000 0x0 0x1000>; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 interrupt-parent = <&plic>; 382 interrupts = <58>; 383 clocks = <&clkcfg CLK_I2C0>; 384 clock-frequency = <100000>; 385 status = "disabled"; 386 }; 387 388 i2c1: i2c@2010b000 { 389 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 390 reg = <0x0 0x2010b000 0x0 0x1000>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 interrupt-parent = <&plic>; 394 interrupts = <61>; 395 clocks = <&clkcfg CLK_I2C1>; 396 clock-frequency = <100000>; 397 status = "disabled"; 398 }; 399 400 can0: can@2010c000 { 401 compatible = "microchip,mpfs-can"; 402 reg = <0x0 0x2010c000 0x0 0x1000>; 403 clocks = <&clkcfg CLK_CAN0>; 404 interrupt-parent = <&plic>; 405 interrupts = <56>; 406 status = "disabled"; 407 }; 408 409 can1: can@2010d000 { 410 compatible = "microchip,mpfs-can"; 411 reg = <0x0 0x2010d000 0x0 0x1000>; 412 clocks = <&clkcfg CLK_CAN1>; 413 interrupt-parent = <&plic>; 414 interrupts = <57>; 415 status = "disabled"; 416 }; 417 418 mac0: ethernet@20110000 { 419 compatible = "microchip,mpfs-macb", "cdns,macb"; 420 reg = <0x0 0x20110000 0x0 0x2000>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 interrupt-parent = <&plic>; 424 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 425 local-mac-address = [00 00 00 00 00 00]; 426 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 427 clock-names = "pclk", "hclk"; 428 resets = <&clkcfg CLK_MAC0>; 429 status = "disabled"; 430 }; 431 432 mac1: ethernet@20112000 { 433 compatible = "microchip,mpfs-macb", "cdns,macb"; 434 reg = <0x0 0x20112000 0x0 0x2000>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 interrupt-parent = <&plic>; 438 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 439 local-mac-address = [00 00 00 00 00 00]; 440 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 441 clock-names = "pclk", "hclk"; 442 resets = <&clkcfg CLK_MAC1>; 443 status = "disabled"; 444 }; 445 446 gpio0: gpio@20120000 { 447 compatible = "microchip,mpfs-gpio"; 448 reg = <0x0 0x20120000 0x0 0x1000>; 449 interrupt-parent = <&plic>; 450 interrupt-controller; 451 #interrupt-cells = <1>; 452 clocks = <&clkcfg CLK_GPIO0>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 status = "disabled"; 456 }; 457 458 gpio1: gpio@20121000 { 459 compatible = "microchip,mpfs-gpio"; 460 reg = <0x0 0x20121000 0x0 0x1000>; 461 interrupt-parent = <&plic>; 462 interrupt-controller; 463 #interrupt-cells = <1>; 464 clocks = <&clkcfg CLK_GPIO1>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 status = "disabled"; 468 }; 469 470 gpio2: gpio@20122000 { 471 compatible = "microchip,mpfs-gpio"; 472 reg = <0x0 0x20122000 0x0 0x1000>; 473 interrupt-parent = <&plic>; 474 interrupt-controller; 475 #interrupt-cells = <1>; 476 clocks = <&clkcfg CLK_GPIO2>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 status = "disabled"; 480 }; 481 482 rtc: rtc@20124000 { 483 compatible = "microchip,mpfs-rtc"; 484 reg = <0x0 0x20124000 0x0 0x1000>; 485 interrupt-parent = <&plic>; 486 interrupts = <80>, <81>; 487 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 488 clock-names = "rtc", "rtcref"; 489 status = "disabled"; 490 }; 491 492 usb: usb@20201000 { 493 compatible = "microchip,mpfs-musb"; 494 reg = <0x0 0x20201000 0x0 0x1000>; 495 interrupt-parent = <&plic>; 496 interrupts = <86>, <87>; 497 clocks = <&clkcfg CLK_USB>; 498 interrupt-names = "dma","mc"; 499 status = "disabled"; 500 }; 501 502 mbox: mailbox@37020000 { 503 compatible = "microchip,mpfs-mailbox"; 504 reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, 505 <0x0 0x37020800 0x0 0x100>; 506 interrupt-parent = <&plic>; 507 interrupts = <96>; 508 #mbox-cells = <1>; 509 status = "disabled"; 510 }; 511 }; 512}; 513
