1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Regents of the University of California
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/cpu.h>
8 #include <linux/ctype.h>
9 #include <linux/init.h>
10 #include <linux/seq_file.h>
11 #include <linux/of.h>
12 #include <asm/acpi.h>
13 #include <asm/cpufeature.h>
14 #include <asm/csr.h>
15 #include <asm/hwcap.h>
16 #include <asm/sbi.h>
17 #include <asm/smp.h>
18 #include <asm/pgtable.h>
19
arch_match_cpu_phys_id(int cpu,u64 phys_id)20 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
21 {
22 return phys_id == cpuid_to_hartid_map(cpu);
23 }
24
25 /*
26 * Returns the hart ID of the given device tree node, or -ENODEV if the node
27 * isn't an enabled and valid RISC-V hart node.
28 */
riscv_of_processor_hartid(struct device_node * node,unsigned long * hart)29 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart)
30 {
31 int cpu;
32
33 *hart = (unsigned long)of_get_cpu_hwid(node, 0);
34 if (*hart == ~0UL) {
35 pr_warn("Found CPU without hart ID\n");
36 return -ENODEV;
37 }
38
39 cpu = riscv_hartid_to_cpuid(*hart);
40 if (cpu < 0)
41 return cpu;
42
43 if (!cpu_possible(cpu))
44 return -ENODEV;
45
46 return 0;
47 }
48
riscv_early_of_processor_hartid(struct device_node * node,unsigned long * hart)49 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart)
50 {
51 const char *isa;
52
53 if (!of_device_is_compatible(node, "riscv")) {
54 pr_warn("Found incompatible CPU\n");
55 return -ENODEV;
56 }
57
58 *hart = (unsigned long)of_get_cpu_hwid(node, 0);
59 if (*hart == ~0UL) {
60 pr_warn("Found CPU without hart ID\n");
61 return -ENODEV;
62 }
63
64 if (!of_device_is_available(node)) {
65 pr_info("CPU with hartid=%lu is not available\n", *hart);
66 return -ENODEV;
67 }
68
69 if (of_property_read_string(node, "riscv,isa-base", &isa))
70 goto old_interface;
71
72 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {
73 pr_warn("CPU with hartid=%lu does not support rv32i", *hart);
74 return -ENODEV;
75 }
76
77 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {
78 pr_warn("CPU with hartid=%lu does not support rv64i", *hart);
79 return -ENODEV;
80 }
81
82 if (!of_property_present(node, "riscv,isa-extensions"))
83 return -ENODEV;
84
85 if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
86 of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
87 of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {
88 pr_warn("CPU with hartid=%lu does not support ima", *hart);
89 return -ENODEV;
90 }
91
92 return 0;
93
94 old_interface:
95 if (!riscv_isa_fallback) {
96 pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"",
97 *hart);
98 return -ENODEV;
99 }
100
101 if (of_property_read_string(node, "riscv,isa", &isa)) {
102 pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
103 *hart);
104 return -ENODEV;
105 }
106
107 if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) {
108 pr_warn("CPU with hartid=%lu does not support rv32ima", *hart);
109 return -ENODEV;
110 }
111
112 if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) {
113 pr_warn("CPU with hartid=%lu does not support rv64ima", *hart);
114 return -ENODEV;
115 }
116
117 return 0;
118 }
119
120 /*
121 * Find hart ID of the CPU DT node under which given DT node falls.
122 *
123 * To achieve this, we walk up the DT tree until we find an active
124 * RISC-V core (HART) node and extract the cpuid from it.
125 */
riscv_of_parent_hartid(struct device_node * node,unsigned long * hartid)126 int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
127 {
128 int rc;
129
130 for (; node; node = node->parent) {
131 if (of_device_is_compatible(node, "riscv")) {
132 rc = riscv_of_processor_hartid(node, hartid);
133 if (!rc)
134 return 0;
135 }
136 }
137
138 return -1;
139 }
140
141 DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
142
riscv_cached_mvendorid(unsigned int cpu_id)143 unsigned long riscv_cached_mvendorid(unsigned int cpu_id)
144 {
145 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
146
147 return ci->mvendorid;
148 }
149 EXPORT_SYMBOL(riscv_cached_mvendorid);
150
riscv_cached_marchid(unsigned int cpu_id)151 unsigned long riscv_cached_marchid(unsigned int cpu_id)
152 {
153 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
154
155 return ci->marchid;
156 }
157 EXPORT_SYMBOL(riscv_cached_marchid);
158
riscv_cached_mimpid(unsigned int cpu_id)159 unsigned long riscv_cached_mimpid(unsigned int cpu_id)
160 {
161 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
162
163 return ci->mimpid;
164 }
165 EXPORT_SYMBOL(riscv_cached_mimpid);
166
riscv_cpuinfo_starting(unsigned int cpu)167 static int riscv_cpuinfo_starting(unsigned int cpu)
168 {
169 struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo);
170
171 #if IS_ENABLED(CONFIG_RISCV_SBI)
172 ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();
173 ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();
174 ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();
175 #elif IS_ENABLED(CONFIG_RISCV_M_MODE)
176 ci->mvendorid = csr_read(CSR_MVENDORID);
177 ci->marchid = csr_read(CSR_MARCHID);
178 ci->mimpid = csr_read(CSR_MIMPID);
179 #else
180 ci->mvendorid = 0;
181 ci->marchid = 0;
182 ci->mimpid = 0;
183 #endif
184
185 return 0;
186 }
187
riscv_cpuinfo_init(void)188 static int __init riscv_cpuinfo_init(void)
189 {
190 int ret;
191
192 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "riscv/cpuinfo:starting",
193 riscv_cpuinfo_starting, NULL);
194 if (ret < 0) {
195 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
196 return ret;
197 }
198
199 return 0;
200 }
201 arch_initcall(riscv_cpuinfo_init);
202
203 #ifdef CONFIG_PROC_FS
204
print_isa(struct seq_file * f)205 static void print_isa(struct seq_file *f)
206 {
207 seq_puts(f, "isa\t\t: ");
208
209 if (IS_ENABLED(CONFIG_32BIT))
210 seq_write(f, "rv32", 4);
211 else
212 seq_write(f, "rv64", 4);
213
214 for (int i = 0; i < riscv_isa_ext_count; i++) {
215 if (!__riscv_isa_extension_available(NULL, riscv_isa_ext[i].id))
216 continue;
217
218 /* Only multi-letter extensions are split by underscores */
219 if (strnlen(riscv_isa_ext[i].name, 2) != 1)
220 seq_puts(f, "_");
221
222 seq_printf(f, "%s", riscv_isa_ext[i].name);
223 }
224
225 seq_puts(f, "\n");
226 }
227
print_mmu(struct seq_file * f)228 static void print_mmu(struct seq_file *f)
229 {
230 const char *sv_type;
231
232 #ifdef CONFIG_MMU
233 #if defined(CONFIG_32BIT)
234 sv_type = "sv32";
235 #elif defined(CONFIG_64BIT)
236 if (pgtable_l5_enabled)
237 sv_type = "sv57";
238 else if (pgtable_l4_enabled)
239 sv_type = "sv48";
240 else
241 sv_type = "sv39";
242 #endif
243 #else
244 sv_type = "none";
245 #endif /* CONFIG_MMU */
246 seq_printf(f, "mmu\t\t: %s\n", sv_type);
247 }
248
c_start(struct seq_file * m,loff_t * pos)249 static void *c_start(struct seq_file *m, loff_t *pos)
250 {
251 if (*pos == nr_cpu_ids)
252 return NULL;
253
254 *pos = cpumask_next(*pos - 1, cpu_online_mask);
255 if ((*pos) < nr_cpu_ids)
256 return (void *)(uintptr_t)(1 + *pos);
257 return NULL;
258 }
259
c_next(struct seq_file * m,void * v,loff_t * pos)260 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
261 {
262 (*pos)++;
263 return c_start(m, pos);
264 }
265
c_stop(struct seq_file * m,void * v)266 static void c_stop(struct seq_file *m, void *v)
267 {
268 }
269
c_show(struct seq_file * m,void * v)270 static int c_show(struct seq_file *m, void *v)
271 {
272 unsigned long cpu_id = (unsigned long)v - 1;
273 struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id);
274 struct device_node *node;
275 const char *compat;
276
277 seq_printf(m, "processor\t: %lu\n", cpu_id);
278 seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id));
279 print_isa(m);
280 print_mmu(m);
281
282 if (acpi_disabled) {
283 node = of_get_cpu_node(cpu_id, NULL);
284
285 if (!of_property_read_string(node, "compatible", &compat) &&
286 strcmp(compat, "riscv"))
287 seq_printf(m, "uarch\t\t: %s\n", compat);
288
289 of_node_put(node);
290 }
291
292 seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);
293 seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);
294 seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);
295 seq_puts(m, "\n");
296
297 return 0;
298 }
299
300 const struct seq_operations cpuinfo_op = {
301 .start = c_start,
302 .next = c_next,
303 .stop = c_stop,
304 .show = c_show
305 };
306
307 #endif /* CONFIG_PROC_FS */
308
