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/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/
Dti,c64x+megamod-pic.txt1 C6X Interrupt Chips
4 * C64X+ Core Interrupt Controller
6 The core interrupt controller provides 16 prioritized interrupts to the
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
14 - #interrupt-cells: <1>
16 Interrupt Specifier Definition
18 Single cell specifying the core interrupt priority level (4-15) where
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
[all …]
Dmrvl,intc.txt1 * Marvell MMP Interrupt controller
6 - reg : Address and length of the register set of the interrupt controller.
7 If the interrupt controller is intc, address and length means the range
8 of the whole interrupt controller. If the interrupt controller is mux-intc,
10 range of intc. mux-intc is secondary interrupt controller.
11 - reg-names : Name of the register set of the interrupt controller. It's
12 only required in mux-intc interrupt controller.
13 - interrupts : Should be the port interrupt shared by mux interrupts. It's
14 only required in mux-intc interrupt controller.
15 - interrupt-controller : Identifies the node as an interrupt controller.
[all …]
Dsamsung,exynos4210-combiner.txt1 * Samsung Exynos Interrupt Combiner Controller
3 Samsung's Exynos4 architecture includes a interrupt combiner controller which
4 can combine interrupt sources as a group and provide a single interrupt request
5 for the group. The interrupt request from each group are connected to a parent
6 interrupt controller, such as GIC in case of Exynos4210.
8 The interrupt combiner controller consists of multiple combiners. Up to eight
9 interrupt sources can be connected to a combiner. The combiner outputs one
10 combined interrupt for its eight interrupt sources. The combined interrupt
11 is usually connected to a parent interrupt controller.
13 A single node in the device tree is used to describe the interrupt combiner
[all …]
Dmarvell,icu.txt1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
[all …]
Dinterrupts.txt1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
[all …]
Dmarvell,orion-intc.txt1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
[all …]
Dimg,meta-intc.txt8 - compatible: Specifies the compatibility list for the interrupt controller.
11 - num-banks: Specifies the number of interrupt banks (each of which can
12 handle 32 interrupt sources).
14 - interrupt-controller: The presence of this property identifies the node
15 as an interrupt controller. No property value shall be defined.
17 - #interrupt-cells: Specifies the number of cells needed to encode an
18 interrupt source. The type shall be a <u32> and the value shall be 2.
22 'interrupt-map' nodes do not have to specify a parent unit address.
28 * Interrupt Specifier Definition
30 Interrupt specifiers consists of 2 cells encoded as follows:
[all …]
Dbrcm,bcm7120-l2-intc.txt1 Broadcom BCM7120-style Level 2 interrupt controller
3 This interrupt controller hardware is a second level interrupt controller that
4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
7 Such an interrupt controller has the following hardware design:
9 - outputs multiple interrupts signals towards its interrupt controller parent
12 directly output an interrupt signal towards the interrupt controller parent,
13 or if they will output an interrupt signal at this 2nd level interrupt
20 - not all bits within the interrupt controller actually map to an interrupt
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
[all …]
Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
19 interrupt source. The value shall be 2.
21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
[all …]
Dimg,pdc-intc.txt1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
5 lines which can wake the system, and are passed on through output interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/powerpc/fsl/
Dmpic.txt2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/include/ivsrcid/dcn/
Dirqsrcs_dcn_1_0.h78 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERF…
81 #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERF…
84 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON…
87 #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON…
90 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON…
93 #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON…
96 #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT…
102 #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU…
105 #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY…
108 #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY…
[all …]
/Linux-v5.4/arch/powerpc/boot/dts/
Dfsp2.dts64 #interrupt-cells = <2>;
66 interrupt-controller;
76 #interrupt-cells = <2>;
79 interrupt-controller;
82 interrupt-parent = <&UIC0>;
90 #interrupt-cells = <2>;
93 interrupt-controller;
96 interrupt-parent = <&UIC0>;
104 #interrupt-cells = <2>;
107 interrupt-controller;
[all …]
/Linux-v5.4/arch/mips/boot/dts/brcm/
Dbcm7358.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
Dbcm7360.dtsi24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
28 interrupt-controller;
29 #interrupt-cells = <1>;
53 periph_intc: interrupt-controller@411400 {
57 interrupt-controller;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
67 interrupt-controller;
[all …]
Dbcm7346.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
Dbcm7362.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@411400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
Dbcm7425.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@41a400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@403000 {
73 interrupt-controller;
[all …]
Dbcm7435.dtsi42 cpu_intc: interrupt-controller {
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
47 #interrupt-cells = <1>;
71 periph_intc: interrupt-controller@41b500 {
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&cpu_intc>;
83 sun_l2_intc: interrupt-controller@403000 {
86 interrupt-controller;
[all …]
Dbcm7125.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
Dbcm7420.dtsi30 cpu_intc: interrupt-controller {
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
35 #interrupt-cells = <1>;
59 periph_intc: interrupt-controller@441400 {
63 interrupt-controller;
64 #interrupt-cells = <1>;
66 interrupt-parent = <&cpu_intc>;
70 sun_l2_intc: interrupt-controller@401800 {
73 interrupt-controller;
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dexynos5410-pinctrl.dtsi16 interrupt-controller;
17 #interrupt-cells = <2>;
24 interrupt-controller;
25 #interrupt-cells = <2>;
32 interrupt-controller;
33 #interrupt-cells = <2>;
40 interrupt-controller;
41 #interrupt-cells = <2>;
48 interrupt-controller;
49 #interrupt-cells = <2>;
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/pci/
Dxilinx-pcie.txt6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
14 PCI interface to interrupt numbers.
23 Interrupt controller child node
26 - interrupt-controller: identifies the node as an interrupt controller
29 - #interrupt-cells: specifies the number of cells needed to encode an
30 interrupt source. The value must be 1.
[all …]
Dxilinx-nwl-pcie.txt7 - #interrupt-cells: specifies the number of cells needed to encode an
8 interrupt source. The value must be 1.
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 "msi1, msi0": interrupt asserted when an MSI is received
19 "intx": interrupt asserted when a legacy interrupt is received
20 "misc": interrupt asserted when miscellaneous interrupt is received
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
22 mapping of the PCI interface to interrupt numbers.
29 - legacy-interrupt-controller: Interrupt controller device node for Legacy
[all …]
/Linux-v5.4/arch/mips/boot/dts/ingenic/
Djz4770.dtsi10 cpuintc: interrupt-controller {
12 #interrupt-cells = <1>;
13 interrupt-controller;
14 compatible = "mti,cpu-interrupt-controller";
17 intc: interrupt-controller@10001000 {
21 interrupt-controller;
22 #interrupt-cells = <1>;
24 interrupt-parent = <&cpuintc>;
63 interrupt-controller;
64 #interrupt-cells = <1>;
[all …]

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