Lines Matching full:interrupt

2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29   - interrupt-controller
32       Definition: Specifies that this node is an interrupt
35   - #interrupt-cells
38       Definition: Shall be 2 or 4.  A value of 2 means that interrupt
39           specifiers do not contain the interrupt-type or type-specific
52           the boot program has initialized all interrupt source
57           that any initialization related to interrupt sources shall
73   - last-interrupt-source
80 INTERRUPT SPECIFIER DEFINITION
82   Interrupt specifiers consists of 4 cells encoded as
85    <1st-cell>   interrupt-number
87                 Identifies the interrupt source.  The meaning
88                 depends on the type of interrupt.
90                 Note: If the interrupt-type cell is undefined
91                 (i.e. #interrupt-cells = 2), this cell
93                 interrupt-type 0-- i.e. an external or
94                 normal SoC device interrupt.
102    <3rd-cell>   interrupt-type
106                   0 = external or normal SoC device interrupt
108                       The interrupt-number cell contains
109                       the SoC device interrupt number.  The
111                       interrupt-number is derived from the
113                       the "Interrupt Source Configuration Registers".
116                       region.   So interrupt 0 is at offset 0x0,
117                       interrupt 1 is at offset 0x20, and so on.
119                   1 = error interrupt
121                       The interrupt-number cell contains
122                       the SoC device interrupt number for
123                       the error interrupt.  The type-specific
125                       interrupt number.
127                   2 = MPIC inter-processor interrupt (IPI)
129                       The interrupt-number cell identifies
133                   3 = MPIC timer interrupt
135                       The interrupt-number cell identifies
143                  - For interrupt-type 1 (error interrupt),
145                    bit number of the error interrupt in the
146                    Error Interrupt Summary Register.
150 	 * mpic interrupt controller with 4 cells per specifier
154 		interrupt-controller;
155 		#interrupt-cells = <4>;
163 	 * interrupt number of 27.  As per the reference manual
164 	 * this corresponds to interrupt source configuration
167 	 * The interrupt source configuration registers begin
170 	 * To compute the interrupt specifier interrupt number
174 	 * The interrupt source configuration registers begin
185 		interrupt-parent = <&mpic>;
193 	 *  MPIC IPI interrupts.  Note the interrupt
208 	 *  global timers.  Note the interrupt
222 	 * Definition of an error interrupt (interrupt type 1).
223 	 * SoC interrupt number is 16 and the specific error
224          * interrupt bit in the error interrupt summary register