| /Linux-v5.15/drivers/gpu/drm/i915/gt/ |
| D | gen7_renderclear.c | 1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
60 case 1: in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
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| D | gen6_engine_cs.c | 1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
19 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
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| D | selftest_lrc.c | 1 // SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
30 return __vm_create_scratch_for_read_pinned(>->ggtt->vm, PAGE_SIZE); in create_scratch()
52 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
63 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
67 return -ETIME; in wait_for_submit()
70 } while (1); in wait_for_submit()
76 i915_ggtt_offset(ce->engine->status_page.vma) + in emit_semaphore_signal()
79 u32 *cs; in emit_semaphore_signal() local
85 cs = intel_ring_begin(rq, 4); in emit_semaphore_signal()
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| D | gen8_engine_cs.c | 1 // SPDX-License-Identifier: MIT
15 u32 *cs, flags = 0; in gen8_emit_flush_rcs() local
41 if (GRAPHICS_VER(rq->engine->i915) == 9) in gen8_emit_flush_rcs()
45 if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_C0)) in gen8_emit_flush_rcs()
57 cs = intel_ring_begin(rq, len); in gen8_emit_flush_rcs()
58 if (IS_ERR(cs)) in gen8_emit_flush_rcs()
59 return PTR_ERR(cs); in gen8_emit_flush_rcs()
62 cs = gen8_emit_pipe_control(cs, 0, 0); in gen8_emit_flush_rcs()
65 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, in gen8_emit_flush_rcs()
68 cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); in gen8_emit_flush_rcs()
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| D | selftest_engine_pm.c | 1 // SPDX-License-Identifier: GPL-2.0
23 return *a - *b; in cmp_u64()
29 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
32 static u32 *emit_wait(u32 *cs, u32 offset, int op, u32 value) in emit_wait() argument
34 *cs++ = MI_SEMAPHORE_WAIT | in emit_wait()
38 *cs++ = value; in emit_wait()
39 *cs++ = offset; in emit_wait()
40 *cs++ = 0; in emit_wait()
42 return cs; in emit_wait()
45 static u32 *emit_store(u32 *cs, u32 offset, u32 value) in emit_store() argument
[all …]
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| D | gen8_engine_cs.h | 1 /* SPDX-License-Identifier: MIT */
34 u32 *gen8_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
35 u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs);
37 u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
38 u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
39 u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs);
47 batch[1] = flags1; in __gen8_emit_pipe_control()
64 __gen8_emit_write_rcs(u32 *cs, u32 value, u32 offset, u32 flags0, u32 flags1) in __gen8_emit_write_rcs() argument
66 *cs++ = GFX_OP_PIPE_CONTROL(6) | flags0; in __gen8_emit_write_rcs()
67 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE; in __gen8_emit_write_rcs()
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| /Linux-v5.15/Documentation/gpu/rfc/ |
| D | i915_parallel_execbuf.h | 1 /* SPDX-License-Identifier: MIT */
9 * struct drm_i915_context_engines_parallel_submit - Configure engine for
22 * context if each context maps to more than 1 physical engine (e.g. context is
30 * Returns -EINVAL if hardware context placement configuration is invalid or if
33 * Returns -ENODEV if extension isn't supported on the platform / submission
36 * .. code-block:: none
38 * Example 1 pseudo code:
39 * CS[X] = generic engine of same class, logical instance X
42 * set_parallel(engine_index=0, width=2, num_siblings=1,
43 * engines=CS[0],CS[1])
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| /Linux-v5.15/drivers/memory/ |
| D | stm32-fmc2-ebi.c | 1 // SPDX-License-Identifier: GPL-2.0
30 #define FMC2_BCR_MUXEN BIT(1)
99 FMC2_REG_BCR = 1,
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
188 return -EINVAL; in stm32_fmc2_ebi_check_mux()
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| D | omap-gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
31 #include <linux/omap-gpmc.h>
35 #include <linux/platform_data/mtd-nand-omap2.h>
37 #define DEVICE_NAME "omap-gpmc"
79 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
95 * The first 1MB of GPMC address space is typically mapped to
136 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
137 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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| /Linux-v5.15/drivers/scsi/ |
| D | myrs.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
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| /Linux-v5.15/kernel/time/ |
| D | clocksource.c | 1 // SPDX-License-Identifier: GPL-2.0+
20 #include "tick-internal.h"
24 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
35 * NSEC_PER_SEC == 1GHz and @from is the counter frequency. For clock
58 tmp >>=1; in clocks_calc_mult_shift()
59 sftacc--; in clocks_calc_mult_shift()
66 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
78 /*[Clocksource internal variables]---------
88 * Name of the user-specified clocksource.
100 * Also a default for cs->uncertainty_margin when registering clocks.
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| /Linux-v5.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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| D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
29 maxItems: 1
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| /Linux-v5.15/include/linux/mfd/syscon/ |
| D | atmel-smc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
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| /Linux-v5.15/arch/m68k/include/asm/ |
| D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
[all …]
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| D | m5407sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
58 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
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| D | m5206sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
58 #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59 #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
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| /Linux-v5.15/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
29 #define FUSE_INT_REQ_BIT (1ULL << 0)
30 #define FUSE_REQ_ID_STEP (1ULL << 1)
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
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| /Linux-v5.15/drivers/misc/habanalabs/common/ |
| D | hw_queue.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
13 * hl_queue_add_ptr - add to pi or ci and checks if it wraps around
23 ptr &= ((HL_QUEUE_LENGTH << 1) - 1); in hl_hw_queue_add_ptr()
28 return atomic_read(ci) & ((queue_len << 1) - 1); in queue_ci_get()
33 int delta = (q->pi - queue_ci_get(&q->ci, queue_len)); in queue_free_slots()
36 return (queue_len - delta); in queue_free_slots()
38 return (abs(delta) - queue_len); in queue_free_slots()
41 void hl_hw_queue_update_ci(struct hl_cs *cs) in hl_hw_queue_update_ci() argument
43 struct hl_device *hdev = cs->ctx->hdev; in hl_hw_queue_update_ci()
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| D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
18 * enum hl_cs_wait_status - cs wait status
19 * @CS_WAIT_STATUS_BUSY: cs was not completed yet
20 * @CS_WAIT_STATUS_COMPLETED: cs completed
21 * @CS_WAIT_STATUS_GONE: cs completed but fence is already gone
39 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
41 dev_dbg(hdev->dev, "reset sob id %u\n", hw_sob->sob_id); in hl_sob_reset()
43 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
45 hw_sob->need_reset = false; in hl_sob_reset()
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| /Linux-v5.15/drivers/mfd/ |
| D | atmel-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
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| /Linux-v5.15/drivers/spi/ |
| D | spi-fsl-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/dma-mapping.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
50 #define TYPE_GRLIB 1
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
83 if (match && match->data) in fsl_spi_get_type()
84 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
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| /Linux-v5.15/Documentation/devicetree/bindings/spi/ |
| D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-[0-9a-f])*$"
22 "#address-cells":
23 enum: [0, 1]
25 "#size-cells":
28 cs-gpios:
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| /Linux-v5.15/drivers/net/slip/ |
| D | slhc.c | 21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
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| /Linux-v5.15/arch/mips/netlogic/xlr/ |
| D | platform-flash.c | 72 .name = "physmap-flash",
88 int cs; member
99 FLASH_NAND_CLE(nand_priv.cs), cmd); in xlr_nand_ctrl()
102 FLASH_NAND_ALE(nand_priv.cs), cmd); in xlr_nand_ctrl()
107 .nr_chips = 1,
125 .id = -1,
143 uint64_t flash_map_base, int cs, struct resource *res) in setup_flash_resource() argument
147 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); in setup_flash_resource()
148 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); in setup_flash_resource()
150 res->start = flash_map_base + ((unsigned long)base << 16); in setup_flash_resource()
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