Lines Matching +full:cs +full:- +full:1
1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
60 case 1: in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
71 bv->surface_width = 32 * 2 * 16; in batch_get_defaults()
73 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
75 case 1: /* including vlv */ in batch_get_defaults()
76 bv->max_threads = 36; in batch_get_defaults()
79 bv->max_threads = 128; in batch_get_defaults()
82 bv->surface_height = 16 * 8; in batch_get_defaults()
83 bv->surface_width = 32 * 16; in batch_get_defaults()
85 bv->state_start = round_up(SZ_1K + num_primitives(bv) * 64, SZ_4K); in batch_get_defaults()
86 bv->surface_start = bv->state_start + SZ_4K; in batch_get_defaults()
87 bv->size = bv->surface_start + bv->surface_height * bv->surface_width; in batch_get_defaults()
94 bc->vma = vma; in batch_init()
95 bc->offset = offset; in batch_init()
96 bc->start = start + bc->offset / sizeof(*bc->start); in batch_init()
97 bc->end = bc->start; in batch_init()
98 bc->max_items = max_bytes / sizeof(*bc->start); in batch_init()
101 static u32 batch_offset(const struct batch_chunk *bc, u32 *cs) in batch_offset() argument
103 return (cs - bc->start) * sizeof(*bc->start) + bc->offset; in batch_offset()
108 return bc->vma->node.start; in batch_addr()
113 GEM_BUG_ON((bc->end - bc->start) >= bc->max_items); in batch_add()
114 *bc->end++ = d; in batch_add()
122 u32 *end = PTR_ALIGN(bc->end, align); in batch_alloc_items()
124 memset32(bc->end, 0, end - bc->end); in batch_alloc_items()
125 bc->end = end; in batch_alloc_items()
128 map = bc->end; in batch_alloc_items()
129 bc->end += items; in batch_alloc_items()
136 GEM_BUG_ON(!IS_ALIGNED(bytes, sizeof(*bc->start))); in batch_alloc_bytes()
137 return batch_alloc_items(bc, align, bytes / sizeof(*bc->start)); in batch_alloc_bytes()
145 u32 surface_h = bv->surface_height; in gen7_fill_surface_state()
146 u32 surface_w = bv->surface_width; in gen7_fill_surface_state()
147 u32 *cs = batch_alloc_items(state, 32, 8); in gen7_fill_surface_state() local
148 u32 offset = batch_offset(state, cs); in gen7_fill_surface_state()
150 #define SURFACE_2D 1 in gen7_fill_surface_state()
152 #define RENDER_CACHE_READ_WRITE 1 in gen7_fill_surface_state()
154 *cs++ = SURFACE_2D << 29 | in gen7_fill_surface_state()
158 *cs++ = batch_addr(state) + dst_offset; in gen7_fill_surface_state()
160 *cs++ = ((surface_h / 4 - 1) << 16) | (surface_w / 4 - 1); in gen7_fill_surface_state()
161 *cs++ = surface_w; in gen7_fill_surface_state()
162 *cs++ = 0; in gen7_fill_surface_state()
163 *cs++ = 0; in gen7_fill_surface_state()
164 *cs++ = 0; in gen7_fill_surface_state()
167 *cs++ = SHADER_CHANNELS(4, 5, 6, 7); in gen7_fill_surface_state()
168 batch_advance(state, cs); in gen7_fill_surface_state()
178 gen7_fill_surface_state(state, bv->surface_start, bv); in gen7_fill_binding_table()
179 u32 *cs = batch_alloc_items(state, 32, 8); in gen7_fill_binding_table() local
180 u32 offset = batch_offset(state, cs); in gen7_fill_binding_table()
182 *cs++ = surface_start - state->offset; in gen7_fill_binding_table()
183 *cs++ = 0; in gen7_fill_binding_table()
184 *cs++ = 0; in gen7_fill_binding_table()
185 *cs++ = 0; in gen7_fill_binding_table()
186 *cs++ = 0; in gen7_fill_binding_table()
187 *cs++ = 0; in gen7_fill_binding_table()
188 *cs++ = 0; in gen7_fill_binding_table()
189 *cs++ = 0; in gen7_fill_binding_table()
190 batch_advance(state, cs); in gen7_fill_binding_table()
212 gen7_fill_kernel_data(state, kernel->data, kernel->size); in gen7_fill_interface_descriptor()
214 u32 *cs = batch_alloc_items(state, 32, 8 * count); in gen7_fill_interface_descriptor() local
215 u32 offset = batch_offset(state, cs); in gen7_fill_interface_descriptor()
217 *cs++ = kernel_offset; in gen7_fill_interface_descriptor()
218 *cs++ = (1 << 7) | (1 << 13); in gen7_fill_interface_descriptor()
219 *cs++ = 0; in gen7_fill_interface_descriptor()
220 *cs++ = (binding_table - state->offset) | 1; in gen7_fill_interface_descriptor()
221 *cs++ = 0; in gen7_fill_interface_descriptor()
222 *cs++ = 0; in gen7_fill_interface_descriptor()
223 *cs++ = 0; in gen7_fill_interface_descriptor()
224 *cs++ = 0; in gen7_fill_interface_descriptor()
226 /* 1 - 63dummy idds */ in gen7_fill_interface_descriptor()
227 memset32(cs, 0x00, (count - 1) * 8); in gen7_fill_interface_descriptor()
228 batch_advance(state, cs + (count - 1) * 8); in gen7_fill_interface_descriptor()
237 u32 *cs = batch_alloc_items(batch, 0, 10); in gen7_emit_state_base_address() local
239 *cs++ = STATE_BASE_ADDRESS | (10 - 2); in gen7_emit_state_base_address()
241 *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
243 *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
245 *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
247 *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
249 *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
252 *cs++ = 0; in gen7_emit_state_base_address()
253 *cs++ = BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
254 *cs++ = 0; in gen7_emit_state_base_address()
255 *cs++ = BASE_ADDRESS_MODIFY; in gen7_emit_state_base_address()
256 batch_advance(batch, cs); in gen7_emit_state_base_address()
265 u32 threads = bv->max_threads - 1; in gen7_emit_vfe_state()
266 u32 *cs = batch_alloc_items(batch, 32, 8); in gen7_emit_vfe_state() local
268 *cs++ = MEDIA_VFE_STATE | (8 - 2); in gen7_emit_vfe_state()
271 *cs++ = 0; in gen7_emit_vfe_state()
274 *cs++ = threads << 16 | 1 << 8 | mode << 2; in gen7_emit_vfe_state()
276 *cs++ = 0; in gen7_emit_vfe_state()
279 *cs++ = urb_size << 16 | curbe_size; in gen7_emit_vfe_state()
282 *cs++ = 0; in gen7_emit_vfe_state()
283 *cs++ = 0; in gen7_emit_vfe_state()
284 *cs++ = 0; in gen7_emit_vfe_state()
285 batch_advance(batch, cs); in gen7_emit_vfe_state()
293 u32 *cs = batch_alloc_items(batch, 8, 4); in gen7_emit_interface_descriptor_load() local
295 *cs++ = MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2); in gen7_emit_interface_descriptor_load()
296 *cs++ = 0; in gen7_emit_interface_descriptor_load()
297 *cs++ = count * 8 * sizeof(*cs); in gen7_emit_interface_descriptor_load()
300 * interface descriptor address - it is relative to the dynamics base in gen7_emit_interface_descriptor_load()
303 *cs++ = interface_descriptor; in gen7_emit_interface_descriptor_load()
304 batch_advance(batch, cs); in gen7_emit_interface_descriptor_load()
314 u32 *cs; in gen7_emit_media_object() local
316 cs = batch_alloc_items(batch, 8, pkt); in gen7_emit_media_object()
318 *cs++ = MEDIA_OBJECT | (pkt - 2); in gen7_emit_media_object()
321 *cs++ = 0; in gen7_emit_media_object()
324 *cs++ = 0; in gen7_emit_media_object()
325 *cs++ = 0; in gen7_emit_media_object()
328 *cs++ = 0; in gen7_emit_media_object()
329 *cs++ = 0; in gen7_emit_media_object()
332 *cs++ = y_offset << 16 | x_offset; in gen7_emit_media_object()
333 *cs++ = 0; in gen7_emit_media_object()
334 *cs++ = GT3_INLINE_DATA_DELAYS; in gen7_emit_media_object()
336 batch_advance(batch, cs); in gen7_emit_media_object()
341 u32 *cs = batch_alloc_items(batch, 0, 4); in gen7_emit_pipeline_flush() local
343 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_emit_pipeline_flush()
344 *cs++ = PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH | in gen7_emit_pipeline_flush()
348 *cs++ = 0; in gen7_emit_pipeline_flush()
349 *cs++ = 0; in gen7_emit_pipeline_flush()
351 batch_advance(batch, cs); in gen7_emit_pipeline_flush()
356 u32 *cs = batch_alloc_items(batch, 0, 10); in gen7_emit_pipeline_invalidate() local
359 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
360 *cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD | in gen7_emit_pipeline_invalidate()
362 *cs++ = 0; in gen7_emit_pipeline_invalidate()
363 *cs++ = 0; in gen7_emit_pipeline_invalidate()
364 *cs++ = 0; in gen7_emit_pipeline_invalidate()
366 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen7_emit_pipeline_invalidate()
367 *cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE; in gen7_emit_pipeline_invalidate()
368 *cs++ = 0; in gen7_emit_pipeline_invalidate()
369 *cs++ = 0; in gen7_emit_pipeline_invalidate()
370 *cs++ = 0; in gen7_emit_pipeline_invalidate()
372 batch_advance(batch, cs); in gen7_emit_pipeline_invalidate()
379 struct drm_i915_private *i915 = vma->vm->i915; in emit_batch()
380 const unsigned int desc_count = 1; in emit_batch()
381 const unsigned int urb_size = 1; in emit_batch()
386 batch_init(&cmds, vma, start, 0, bv->state_start); in emit_batch()
387 batch_init(&state, vma, start, bv->state_start, SZ_4K); in emit_batch()
419 /* Set the clear-residual kernel state */ in emit_batch()
420 gen7_emit_vfe_state(&cmds, bv, urb_size - 1, 0, 0); in emit_batch()
436 batch_get_defaults(engine->i915, &bv); in gen7_setup_clear_gpr_bb()
440 GEM_BUG_ON(vma->obj->base.size < bv.size); in gen7_setup_clear_gpr_bb()
442 batch = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); in gen7_setup_clear_gpr_bb()
448 i915_gem_object_flush_map(vma->obj); in gen7_setup_clear_gpr_bb()
449 __i915_gem_object_release_map(vma->obj); in gen7_setup_clear_gpr_bb()