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/Linux-v5.15/drivers/net/ethernet/qualcomm/
Dqca_7k.h35 #define QCA7K_SPI_WRITE (0 << 15)
37 #define QCA7K_SPI_EXTERNAL (0 << 14)
41 #define QCASPI_HW_BUF_LEN 0xC5B
44 #define SPI_REG_BFR_SIZE 0x0100
45 #define SPI_REG_WRBUF_SPC_AVA 0x0200
46 #define SPI_REG_RDBUF_BYTE_AVA 0x0300
47 #define SPI_REG_SPI_CONFIG 0x0400
48 #define SPI_REG_SPI_STATUS 0x0500
49 #define SPI_REG_INTR_CAUSE 0x0C00
50 #define SPI_REG_INTR_ENABLE 0x0D00
[all …]
/Linux-v5.15/drivers/regulator/
Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/Linux-v5.15/drivers/net/wireless/broadcom/b43/
Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
Dphy_g.c75 {.att = 3,.with_padmix = 0,}, in generate_rfatt_list()
76 {.att = 1,.with_padmix = 0,}, in generate_rfatt_list()
77 {.att = 5,.with_padmix = 0,}, in generate_rfatt_list()
78 {.att = 7,.with_padmix = 0,}, in generate_rfatt_list()
79 {.att = 9,.with_padmix = 0,}, in generate_rfatt_list()
80 {.att = 2,.with_padmix = 0,}, in generate_rfatt_list()
81 {.att = 0,.with_padmix = 0,}, in generate_rfatt_list()
82 {.att = 4,.with_padmix = 0,}, in generate_rfatt_list()
83 {.att = 6,.with_padmix = 0,}, in generate_rfatt_list()
84 {.att = 8,.with_padmix = 0,}, in generate_rfatt_list()
[all …]
/Linux-v5.15/arch/arm/boot/dts/
Ddra76x.dtsi14 ranges = <0x0 0x42c00000 0x2000>;
17 reg = <0x42c01900 0x4>,
18 <0x42c01904 0x4>,
19 <0x42c01908 0x4>;
24 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_ADC_CLKCTRL 0>;
29 reg = <0x1a00 0x4000>, <0x0 0x18FC>;
37 bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
45 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
47 reg = <0x1b0000 0x4>,
48 <0x1b0010 0x4>;
[all …]
/Linux-v5.15/arch/mips/include/asm/mach-ar7/
Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
/Linux-v5.15/drivers/block/
Dswim_asm.S17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
/Linux-v5.15/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/Linux-v5.15/drivers/net/wireless/broadcom/b43legacy/
Dradio.c30 0x0002, 0x0003, 0x0001, 0x000F,
31 0x0006, 0x0007, 0x0005, 0x000F,
32 0x000A, 0x000B, 0x0009, 0x000F,
33 0x000E, 0x000F, 0x000D, 0x000F,
41 u16 flipped = 0x0000; in flip_4bit()
43 B43legacy_BUG_ON(!((value & ~0x000F) == 0x0000)); in flip_4bit()
45 flipped |= (value & 0x0001) << 3; in flip_4bit()
46 flipped |= (value & 0x0002) << 1; in flip_4bit()
47 flipped |= (value & 0x0004) >> 1; in flip_4bit()
48 flipped |= (value & 0x0008) >> 3; in flip_4bit()
[all …]
/Linux-v5.15/arch/x86/boot/
Dvideo-vga.c18 { VIDEO_80x25, 80, 25, 0 },
19 { VIDEO_8POINT, 80, 50, 0 },
20 { VIDEO_80x43, 80, 43, 0 },
21 { VIDEO_80x28, 80, 28, 0 },
22 { VIDEO_80x30, 80, 30, 0 },
23 { VIDEO_80x34, 80, 34, 0 },
24 { VIDEO_80x60, 80, 60, 0 },
28 { VIDEO_80x25, 80, 25, 0 },
29 { VIDEO_8POINT, 80, 43, 0 },
33 { VIDEO_80x25, 80, 25, 0 },
[all …]
/Linux-v5.15/arch/arm/plat-orion/
Dpcie.c22 #define PCIE_DEV_ID_OFF 0x0000
23 #define PCIE_CMD_OFF 0x0004
24 #define PCIE_DEV_REV_OFF 0x0008
25 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
26 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
27 #define PCIE_HEADER_LOG_4_OFF 0x0128
28 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + ((n - 1) * 4))
29 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
30 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
31 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
[all …]
/Linux-v5.15/include/video/
Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
/Linux-v5.15/arch/arm/mach-omap2/
Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
/Linux-v5.15/drivers/net/ethernet/microchip/
Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/Linux-v5.15/drivers/net/ethernet/sis/
Dsis190.c40 #define PHY_ID_ANY 0x1f
41 #define MII_REG_ANY 0x1f
55 #define RX_BUF_MASK 0xfff8
57 #define SIS190_REGS_SIZE 0x80
65 #define EhnMIIread 0x0000
66 #define EhnMIIwrite 0x0020
70 #define EhnMIIreq 0x0010
71 #define EhnMIInotDone 0x0010
84 TxControl = 0x00,
85 TxDescStartAddr = 0x04,
[all …]
/Linux-v5.15/drivers/media/pci/cx25821/
Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/Linux-v5.15/drivers/net/wireless/realtek/rtw88/
Drtw8822c.h11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 mac_addr[ETH_ALEN]; /* 0x120 */
28 u8 ltr_cap; /* 0x133 */
33 u8 res0:2; /* 0x144 */
57 u8 res0[0x0e];
62 u8 channel_plan; /* 0xb8 */
66 u8 res2[5]; /* 0xbc */
[all …]
/Linux-v5.15/drivers/mfd/
Dintel_pmc_bxt.c38 #define PLAT_RESOURCE_IPC_INDEX 0
39 #define PLAT_RESOURCE_IPC_SIZE 0x1000
40 #define PLAT_RESOURCE_GCR_OFFSET 0x1000
41 #define PLAT_RESOURCE_GCR_SIZE 0x1000
49 #define PLAT_RESOURCE_ACPI_IO_INDEX 0
57 #define SMI_EN_OFFSET 0x0040
59 #define TCO_BASE_OFFSET 0x0060
62 #define TELEM_PMC_SSRAM_OFFSET 0x1b00
63 #define TELEM_PUNIT_SSRAM_OFFSET 0x1a00
66 #define PMC_NORTHPEAK_CTRL 0xed
[all …]
/Linux-v5.15/arch/m68k/include/asm/
Dmac_via.h22 #define VIA1_BASE (0x50F00000)
23 #define VIA2_BASE (0x50F02000)
24 #define RBV_BASE (0x50F26000)
31 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
39 #define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
44 * on IIfx, "0 means an active request"
46 #define VIA1A_vRev8 0x40 /* Revision 8 board ???
52 * 0=alternate, 1=main.
54 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
56 #define VIA1A_vHeadSel 0x20 /* Head select for IWM.
[all …]
/Linux-v5.15/drivers/net/wireless/realtek/rtlwifi/
Ddebug.c80 int max = 0xff; in rtl_debug_get_mac_page()
82 for (n = 0; n <= max; ) { in rtl_debug_get_mac_page()
84 for (i = 0; i < 4 && n <= max; i++, n += 4) in rtl_debug_get_mac_page()
89 return 0; in rtl_debug_get_mac_page()
98 RTL_DEBUG_IMPL_MAC_SERIES(0, 0x0000);
99 RTL_DEBUG_IMPL_MAC_SERIES(1, 0x0100);
100 RTL_DEBUG_IMPL_MAC_SERIES(2, 0x0200);
101 RTL_DEBUG_IMPL_MAC_SERIES(3, 0x0300);
102 RTL_DEBUG_IMPL_MAC_SERIES(4, 0x0400);
103 RTL_DEBUG_IMPL_MAC_SERIES(5, 0x0500);
[all …]
/Linux-v5.15/sound/soc/intel/atom/
Dsst-mfld-dsp.h20 #define SST_MAILBOX_SIZE 0x0400
21 #define SST_MAILBOX_SEND 0x0000
22 #define SST_TIME_STAMP 0x1800
23 #define SST_TIME_STAMP_MRFLD 0x800
24 #define SST_RESERVED_OFFSET 0x1A00
25 #define SST_SCU_LPE_MAILBOX 0x1000
26 #define SST_LPE_SCU_MAILBOX 0x1400
28 #define PROCESS_MSG 0x80
34 #define IPC_IA_PREP_LIB_DNLD 0x01
35 #define IPC_IA_LIB_DNLD_CMPLT 0x02
[all …]
/Linux-v5.15/include/uapi/linux/
Dmdio.h70 #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
71 #define MDIO_PMA_LASI_TXCTRL 0x9001 /* TX_ALARM control */
72 #define MDIO_PMA_LASI_CTRL 0x9002 /* LASI control */
73 #define MDIO_PMA_LASI_RXSTAT 0x9003 /* RX_ALARM status */
74 #define MDIO_PMA_LASI_TXSTAT 0x9004 /* TX_ALARM status */
75 #define MDIO_PMA_LASI_STAT 0x9005 /* LASI status */
81 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
85 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001
92 #define MDIO_AN_CTRL1_XNP 0x2000 /* Enable extended next page */
93 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 /* Stop the clock during LPI */
[all …]
/Linux-v5.15/drivers/gpu/drm/r128/
Dr128_drv.h64 #define DRIVER_PATCHLEVEL 0
187 #define R128_AUX_SC_CNTL 0x1660
188 # define R128_AUX1_SC_EN (1 << 0)
189 # define R128_AUX1_SC_MODE_OR (0 << 1)
192 # define R128_AUX2_SC_MODE_OR (0 << 3)
195 # define R128_AUX3_SC_MODE_OR (0 << 5)
197 #define R128_AUX1_SC_LEFT 0x1664
198 #define R128_AUX1_SC_RIGHT 0x1668
199 #define R128_AUX1_SC_TOP 0x166c
200 #define R128_AUX1_SC_BOTTOM 0x1670
[all …]
/Linux-v5.15/drivers/media/i2c/ccs/
Dsmiapp-reg-defs.h16 #define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
17 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
18 #define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
19 #define SMIAPP_REG_U8_SMIA_VERSION 0x0004
20 #define SMIAPP_REG_U8_FRAME_COUNT 0x0005
21 #define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
22 #define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
23 #define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
24 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
25 #define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
[all …]

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