Lines Matching +full:0 +full:x1a00
22 #define VIA1_BASE (0x50F00000)
23 #define VIA2_BASE (0x50F02000)
24 #define RBV_BASE (0x50F26000)
31 * ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
39 #define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
44 * on IIfx, "0 means an active request"
46 #define VIA1A_vRev8 0x40 /* Revision 8 board ???
52 * 0=alternate, 1=main.
54 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
56 #define VIA1A_vHeadSel 0x20 /* Head select for IWM.
61 #define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
67 * CPU ID: 0=normal IIci, 1=IIci with parity
73 * (with 0x20 being 'disk head select')
75 #define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
78 * 0: Select the 3.6864MHz clock to drive
83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
86 * bit 2: 1=IIci, 0=IIfx
88 * MkLinux sez bit 0 is 'burnin flag' in this case.
89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
90 * inputs, these bits will read 0.
92 #define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
93 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
94 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
95 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
96 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
100 #define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
101 * PWM hardware) 0=enabled.
103 * 0=error, 1=OK. */
104 #define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
106 * 0=enabled. This vSync interrupt shows up
108 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
109 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
110 #define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
111 #define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
118 #define EVRB_XCVR 0x08 /* XCVR_SESSION* */
119 #define EVRB_FULL 0x10 /* VIA_FULL */
120 #define EVRB_SYSES 0x20 /* SYS_SESSION */
121 #define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */
122 #define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */
123 #define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */
124 #define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
130 * MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
136 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
137 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
138 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
139 #define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
140 #define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
141 #define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
142 #define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
143 #define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
147 * 0 0 256 kbit
148 * 0 1 1 Mbit
149 * 1 0 4 Mbit
157 #define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
159 * on IIci, parity test: 0=test mode.
160 * [MkLinux] RBV_PARODD: 1=odd,0=even. */
161 #define VIA2B_vSndJck 0x40 /* External sound jack status.
162 * 0=plug is inserted. On SE/30, always 0 */
163 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
164 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
165 #define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
167 * if AMU, 0=24bit to 32bit translation
171 * on IIci/RBV, cache control. 0=flush cache.
173 #define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
175 #define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
177 #define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
178 * on others, 0=disable processor's instruction
194 /* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
197 #define vBufB 0x0000 /* [VIA/RBV] Register B */
198 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
199 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
200 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
201 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
202 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
203 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
204 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
205 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
206 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
207 #define vSR 0x1400 /* [VIA only] Shift register. */
208 #define vACR 0x1600 /* [VIA only] Auxiliary control register. */
209 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */
213 #define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
214 #define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
215 #define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
219 /* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
222 * setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
226 #define rBufB 0x0000 /* [VIA/RBV] Register B */
227 #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
228 #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
229 #define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
230 #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
231 #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
232 #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
233 #define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
239 #define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
240 #define RBV_MONID 0x38 /* monitor type, as below. */
241 #define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
250 #define IER_SET_BIT(b) (0x80 | (1<<(b)) )
251 #define IER_CLR_BIT(b) (0x7F & (1<<(b)) )
272 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; in rbv_set_video_bpp()
273 if (!rbv_present || val<0) return -1; in rbv_set_video_bpp()
275 return 0; in rbv_set_video_bpp()