Lines Matching +full:0 +full:x1a00
11 u8 res0[0x30]; /* 0x120 */
12 u8 vid[2]; /* 0x150 */
15 u8 mac_addr[ETH_ALEN]; /* 0x157 */
16 u8 res2[0x3d];
20 u8 mac_addr[ETH_ALEN]; /* 0x120 */
28 u8 ltr_cap; /* 0x133 */
33 u8 res0:2; /* 0x144 */
57 u8 res0[0x0e];
62 u8 channel_plan; /* 0xb8 */
66 u8 res2[5]; /* 0xbc */
75 u8 rf_antenna_option; /* 0xc9 */
79 u8 path_a_thermal; /* 0xd0 */
92 u8 res10[0x42];
135 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
137 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
139 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16))
141 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24))
145 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
147 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
149 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
151 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
153 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
155 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8))
157 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
159 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8))
161 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0))
163 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8))
165 #define REG_ANAPARLDO_POW_MAC 0x0029
166 #define BIT_LDOE25_PON BIT(0)
167 #define XCAP_MASK GENMASK(6, 0)
172 #define REG_TXDFIR0 0x808
173 #define REG_DFIRBW 0x810
174 #define REG_ANTMAP0 0x820
175 #define BIT_ANT_PATH GENMASK(1, 0)
176 #define REG_ANTMAP 0x824
177 #define REG_DYMPRITH 0x86c
178 #define REG_DYMENTH0 0x870
179 #define REG_DYMENTH 0x874
180 #define REG_SBD 0x88c
182 #define REG_DYMTHMIN 0x8a4
184 #define REG_TXBWCTL 0x9b0
185 #define REG_TXCLK 0x9b4
187 #define REG_SCOTRK 0xc30
188 #define REG_MRCM 0xc38
189 #define REG_AGCSWSH 0xc44
190 #define REG_ANTWTPD 0xc54
191 #define REG_PT_CHSMO 0xcbc
194 #define REG_ORITXCODE 0x1800
196 #define REG_3WIRE 0x180c
198 #define BIT_3WIRE_TX_EN BIT(0)
200 #define BIT_3WIRE_EN GENMASK(1, 0)
202 #define REG_ANAPAR_A 0x1830
204 #define REG_RFTXEN_GCK_A 0x1864
206 #define REG_DIS_SHARE_RX_A 0x186c
208 #define REG_RXAGCCTL0 0x18ac
211 #define REG_DCKA_I_0 0x18bc
212 #define REG_DCKA_I_1 0x18c0
213 #define REG_DCKA_Q_0 0x18d8
214 #define REG_DCKA_Q_1 0x18dc
216 #define REG_CCKSB 0x1a00
218 #define REG_RXCCKSEL 0x1a04
219 #define REG_BGCTRL 0x1a14
221 #define REG_TXF0 0x1a20
222 #define REG_TXF1 0x1a24
223 #define REG_TXF2 0x1a28
224 #define REG_CCANRX 0x1a2c
227 #define REG_CCK_FACNT 0x1a5c
228 #define REG_CCKTXONLY 0x1a80
230 #define REG_TXF3 0x1a98
231 #define REG_TXF4 0x1a9c
232 #define REG_TXF5 0x1aa0
233 #define REG_TXF6 0x1aac
234 #define REG_TXF7 0x1ab0
235 #define REG_CCK_SOURCE 0x1abc
238 #define REG_NCTL0 0x1b00
240 #define BIT_SUBPAGE GENMASK(3, 0)
241 #define REG_DPD_CTL0_S0 0x1b04
242 #define BIT_GS_PWSF GENMASK(27, 0)
243 #define REG_DPD_CTL1_S0 0x1b08
246 #define REG_IQKSTAT 0x1b10
247 #define REG_IQK_CTL1 0x1b20
252 #define REG_TX_TONE_IDX 0x1b2c
253 #define REG_DPD_LUT0 0x1b44
255 #define REG_DPD_CTL0_S1 0x1b5c
256 #define REG_DPD_CTL1_S1 0x1b60
257 #define REG_DPD_AGC 0x1b67
258 #define REG_TABLE_SEL 0x1b98
262 #define BIT_Q_GAIN GENMASK(11, 0)
263 #define REG_TX_GAIN_SET 0x1b9c
265 #define REG_DPD_CTL0 0x1bb4
266 #define REG_SINGLE_TONE_SW 0x1bb8
268 #define REG_R_CONFIG 0x1bcc
270 #define BIT_IQ_SWITCH GENMASK(5, 0)
271 #define BIT_2G_SWING 0x2d
272 #define BIT_5G_SWING 0x36
273 #define REG_RXSRAM_CTL 0x1bd4
277 #define REG_DPD_CTL11 0x1be4
278 #define REG_DPD_CTL12 0x1be8
279 #define REG_DPD_CTL15 0x1bf4
280 #define REG_DPD_CTL16 0x1bf8
281 #define REG_STAT_RPT 0x1bfc
283 #define BIT_GAPK_RPT0 GENMASK(3, 0)
292 #define REG_TXANT 0x1c28
293 #define REG_IQK_CTRL 0x1c38
294 #define REG_ENCCK 0x1c3c
296 #define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
297 #define REG_CCAMSK 0x1c80
298 #define REG_RSTB 0x1c90
300 #define REG_CH_DELAY_EXTR2 0x1cd0
306 #define REG_RX_BREAK 0x1d2c
308 #define REG_RXFNCTL 0x1d30
309 #define REG_CCA_OFF 0x1d58
311 #define REG_RXIGI 0x1d70
313 #define REG_ENFN 0x1e24
315 #define REG_TXANTSEG 0x1e28
316 #define BIT_ANTSEG GENMASK(3, 0)
317 #define REG_TXLGMAP 0x1e2c
318 #define REG_CCKPATH 0x1e5c
319 #define REG_TX_FIFO 0x1e70
320 #define BIT_STOP_TX GENMASK(3, 0)
321 #define REG_CNT_CTRL 0x1eb4
324 #define REG_OFDM_FACNT 0x2d00
325 #define REG_OFDM_FACNT1 0x2d04
326 #define REG_OFDM_FACNT2 0x2d08
327 #define REG_OFDM_FACNT3 0x2d0c
328 #define REG_OFDM_FACNT4 0x2d10
329 #define REG_OFDM_FACNT5 0x2d20
330 #define REG_RPT_CIP 0x2d9c
331 #define BIT_RPT_CIP_STATUS GENMASK(7, 0)
332 #define REG_OFDM_TXCNT 0x2de0
334 #define REG_ORITXCODE2 0x4100
335 #define REG_3WIRE2 0x410c
336 #define REG_ANAPAR_B 0x4130
337 #define REG_RFTXEN_GCK_B 0x4164
338 #define REG_DIS_SHARE_RX_B 0x416c
340 #define REG_RXAGCCTL 0x41ac
341 #define REG_DCKB_I_0 0x41bc
342 #define REG_DCKB_I_1 0x41c0
343 #define REG_DCKB_Q_0 0x41d8
344 #define REG_DCKB_Q_1 0x41dc
346 #define RF_MODE_TRXAGC 0x00
349 #define BIT_TXAGC GENMASK(4, 0)
350 #define RF_RXAGC_OFFSET 0x19
351 #define RF_BW_TRXBB 0x1a
356 #define RF_TX_GAIN_OFFSET 0x55
359 #define RF_TX_GAIN 0x56
360 #define BIT_GAIN_TXBB GENMASK(4, 0)
361 #define RF_IDAC 0x58
363 #define RF_TX_RESULT 0x5f
366 #define RF_PA 0x60
369 #define RF_TXA_LB_SW 0x63
373 #define RF_RXG_GAIN 0x87
375 #define RF_RXA_MIX_GAIN 0x8a
377 #define RF_EXT_TIA_BW 0x8f
379 #define RF_DIS_BYPASS_TXBB 0x9e
382 #define RF_DEBUG 0xde
387 #define PPG_THERMAL_B 0x1b0
389 #define PPG_2GH_TXAB 0x1d2
390 #define PPG_2G_A_MASK GENMASK(3, 0)
392 #define PPG_2GL_TXAB 0x1d4
393 #define PPG_PABIAS_2GB 0x1d5
394 #define PPG_PABIAS_2GA 0x1d6
395 #define PPG_PABIAS_MASK GENMASK(3, 0)
396 #define PPG_PABIAS_5GB 0x1d7
397 #define PPG_PABIAS_5GA 0x1d8
398 #define PPG_5G_MASK GENMASK(4, 0)
399 #define PPG_5GH1_TXB 0x1db
400 #define PPG_5GH1_TXA 0x1dc
401 #define PPG_5GM2_TXB 0x1df
402 #define PPG_5GM2_TXA 0x1e0
403 #define PPG_5GM1_TXB 0x1e3
404 #define PPG_5GM1_TXA 0x1e4
405 #define PPG_5GL2_TXB 0x1e7
406 #define PPG_5GL2_TXA 0x1e8
407 #define PPG_5GL1_TXB 0x1eb
408 #define PPG_5GL1_TXA 0x1ec
409 #define PPG_2GM_TXAB 0x1ee
410 #define PPG_THERMAL_A 0x1ef