Searched refs:MUX_GATE (Results 1 – 9 of 9) sorted by relevance
743 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",746 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",748 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",750 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",752 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",755 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",757 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",759 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",761 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",764 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",[all …]
488 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,490 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,492 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,494 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,497 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,499 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,501 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,503 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,508 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,[all …]
495 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,498 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,500 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,502 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,504 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,509 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,511 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,513 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,[all …]
353 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,355 MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),356 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),357 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),359 MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),360 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,362 MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),363 MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),365 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),366 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),[all …]
516 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,518 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,520 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,522 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,526 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,528 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,530 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,532 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,536 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,538 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,[all …]
545 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),546 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),548 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),549 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),550 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0050, 16, 4, 23),551 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 24, 4, 31),553 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0060, 0, 3, 7),554 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),555 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0060, 16, 3, 23),556 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 24, 2, 31),[all …]
335 MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),336 MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, 0x0050, 8, 3, 15),337 MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, 0x0050, 16, 2, 23),338 MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, 0x0050, 24, 2, 31),339 MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg, 0x0060, 0, 2, 7),340 MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, 0x0060, 8, 1, 15),341 MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, 0x0060, 16, 2, 23),344 MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents,348 MUX_GATE(CLK_TOP_MUX_MSDC50_0, "msdc50_0_sel", msdc50_0_parents,350 MUX_GATE(CLK_TOP_MUX_MSDC30_1, "msdc30_1_sel", msdc30_1_parents,[all …]
117 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ macro
393 MUX_GATE(CLK_TOP_MBIST_DIAG_SEL, "mbist_diag_sel", mbist_diag_parents,
