Lines Matching refs:MUX_GATE

516 	MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
518 	MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
520 	MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
522 	MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
526 	MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
528 	MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
530 	MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
532 	MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
536 	MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
538 	MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
540 	MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
542 	MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
546 	MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
548 	MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
550 	MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
552 	MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
556 	MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
558 	MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
560 	MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
562 	MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
566 	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
568 	MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
570 	MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
572 	MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
576 	MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
578 	MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
580 	MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
582 	MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
586 	MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
588 	MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
590 	MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,