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Searched refs:CLK_TOP_AUD_INTBUS_SEL (Results 1 – 23 of 23) sorted by relevance

/Linux-v6.1/include/dt-bindings/clock/
Dmt8135-clk.h78 #define CLK_TOP_AUD_INTBUS_SEL 67 macro
Dmt7629-clk.h100 #define CLK_TOP_AUD_INTBUS_SEL 90 macro
Dmt8516-clk.h168 #define CLK_TOP_AUD_INTBUS_SEL 136 macro
Dmt7622-clk.h85 #define CLK_TOP_AUD_INTBUS_SEL 73 macro
Dmediatek,mt6795-clk.h109 #define CLK_TOP_AUD_INTBUS_SEL 98 macro
Dmt6765-clk.h147 #define CLK_TOP_AUD_INTBUS_SEL 112 macro
Dmt8173-clk.h111 #define CLK_TOP_AUD_INTBUS_SEL 101 macro
Dmediatek,mt8365-clk.h87 #define CLK_TOP_AUD_INTBUS_SEL 77 macro
Dmt2712-clk.h148 #define CLK_TOP_AUD_INTBUS_SEL 117 macro
Dmt8192-clk.h40 #define CLK_TOP_AUD_INTBUS_SEL 28 macro
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c479 TOP_MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt8135.c360 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt7629.c526 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt7622.c558 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt8516.c378 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt8167.c550 MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
Dclk-mt2712.c779 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
Dclk-mt6765.c420 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
Dclk-mt8173.c566 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0080, 24, 3, 31),
Dclk-mt8192.c620 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
Dclk-mt8365.c461 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt8192.dtsi332 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
804 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
Dmt8173.dtsi860 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,